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PDF F59L512M81A Data sheet ( Hoja de datos )

Número de pieza F59L512M81A
Descripción 512Mbit (64M x 8) 3.3V NAND Flash Memory
Fabricantes Elite Semiconductor 
Logotipo Elite Semiconductor Logotipo



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ESMT
Flash
FEATURES
Voltage Supply: 2.7V ~ 3.6V
Organization
- Memory Cell Array: (64M + 2M) x 8bit
- Data Register: (2K + 64) x 8bit
Automatic Program and Erase
- Page Program: (2K + 64) Byte
- Block Erase: (128K + 4K) Byte
Page Read Operation
- Page Size: (2K + 64) Byte
- Random Read: 25us (Max.)
- Serial Access: 25ns (Min.)
Memory Cell: 1bit/Memory Cell
Fast Write Cycle Time
- Program time: 250us (Typ.)
- Block Erase time: 2ms (Typ.)
Command/Address/Data Multiplexed I/O Port
Hardware Data Protection
- Program/Erase Lockout During Power Transitions
Reliable CMOS Floating Gate Technology
- ECC Requirement: 4 bit/512 Byte
- Endurance: 100K Program/Erase cycles
- Data Retention: 10 years
F59L512M81A
512Mbit (64M x 8)
3.3V NAND Flash Memory
Command Register Operation
Automatic Page 0 Read at Power-Up Option
- Boot from NAND support
- Automatic Memory Download
NOP: 4 cycles
Cache Program Operation for High Performance Program
Cache Read Operation
Copy-Back Operation
EDO mode
OTP Operation
Bad-Block-Protect
ORDERING INFORMATION
Product ID
F59L512M81A -25TG
Speed
25 ns
Package
48 pin TSOPI
Comments
Pb-free
GENERAL DESCRIPTION
The device is a 64Mx8bit with spare 2Mx8bit capacity. The
device is offered in 3.3V VCC Power Supply. Its NAND cell
provides the most cost-effective solution for the solid state mass
storage market. The memory is divided into blocks that can be
erased independently so it is possible to preserve valid data
while old data is erased.
The device contains 512 blocks, composed by 64 pages
consisting in two NAND structures of 32 series connected Flash
cells. A program operation allows to write the 2,112-Byte page in
typical 300us and an erase operation can be performed in typical
3ms on a 128K-Byte for X8 device block.
Data in the page mode can be read out at 25ns cycle time per
Byte. The I/O pins serve as the ports for address and command
inputs as well as data input/output. The copy back function
allows the optimization of defective blocks management: when a
page program operation fails the data can be directly
programmed in another page inside the same array section
without the time consuming serial data insertion phase. The
cache program feature allows the data insertion in the cache
register while the data register is copied into the Flash array.
This pipelined program operation improves the program
throughput when long files are written inside the memory. A
cache read feature is also implemented. This feature allows to
dramatically improving the read throughput when consecutive
pages have to be streamed out. This device includes extra
feature: Automatic Read at Power Up.
Elite Semiconductor Memory Technology Inc.
Publication Date: May 2014
Revision: 1.0
1/40

1 page




F59L512M81A pdf
ESMT
F59L512M81A
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Rating
Unit
Voltage on any pin relative to VSS
Temperature Under Bias
Storage Temperature
Short Circuit Current
VCC
VIN
VI/O
TBIAS
TSTG
IOS
-0.6 to +4.6
-0.6 to +4.6
-0.6 to VCC + 0.3 (< 4.6)
-40 to +125
-65 to +150
5
V
mA
Note:
1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be
restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
RECOMMENDED OPERATING CONDITIONS
(Voltage reference to GND, TA = 0 to 70)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Supply Voltage
Supply Voltage
VCC 2.7 3.3 3.6 V
VSS 0 0 0 V
DC AND OPERATION CHARACTERISTICS
(Recommended operating conditions otherwise noted)
Parameter
Operating
Current
Page Read with
Serial Access
Program
Erase
Stand-by Current (TTL)
Stand-by Current (CMOS)
Input Leakage Current
Output Leakage Current
Input High Voltage
Input Low Voltage, All inputs
Output High Voltage Level
Output Low Voltage Level
Symbol
ICC1
ICC2
ICC3
ISB1
ISB2
ILI
ILO
VIH(1)
VIL(1)
VOH
VOL
Test Conditions
tRC=25ns, CE =VIL, IOUT=0mA
-
-
CE =VIH, WP =0V/VCC
CE = VCC -0.2, WP =0V/ VCC
VIN=0 to VCC (max)
VOUT=0 to VCC (max)
-
-
IOH=-400uA
IOL=2.1mA
Min.
-
-
-
-
-
-
-
0.8 x VCC
-0.3
2.4
-
Output Low Current (R/ B )
IOL (R / B ) VOL=0.4V
8
Note:
1. VIL can undershoot to -0.4V and VIH can overshoot to VCC+0.4V for durations of 20ns or less.
2. Typical value are measured at VCC =3.3V, TA=25. And not 100% tested.
Typ.
15
15
15
-
10
-
-
-
-
-
-
10
Max. Unit
30 mA
1
50
±10
±10
VCC +0.3
0.2 x VCC
-
0.4
-
mA
uA
uA
uA
V
V
V
V
mA
VALID BLOCK
Symbol
Min.
Typ.
Max.
Unit
NVB 502 - 512 Blocks
Note:
1. The device may include initial invalid blocks when first shipped. Additional invalid blocks may develop while being used. The
number of valid blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain
one or more bad bits which cause status failure during program and erase operation. Do not erase or program factory-marked bad
blocks. Refer to the attached technical notes for appropriate management of initial invalid blocks.
2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block at the time of shipment and is guaranteed to
be a valid block up to 1K program/erase cycles with 4bit/512Byte ECC.
Elite Semiconductor Memory Technology Inc.
Publication Date: May 2014
Revision: 1.0
5/40

5 Page





F59L512M81A arduino
ESMT
F59L512M81A
Error in write or read operation
Within its lifetime, additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual data.
The following possible failure modes should be considered to implement a highly reliable system. In the case of status read failure after
erase or program, block replacement should be done. Because program status fail during a page program does not affect the data of
the other pages in the same block, block replacement can be executed with a page-sized buffer by finding an erased empty block and
reprogramming the current target data and copying the rest of the replaced block. In case of Read, ECC must be employed. To
improve the efficiency of memory space, it is recommended that the read or verification failure due to single bit error be reclaimed by
ECC without any block replacement. The additional block failure rate does not include those reclaimed blocks.
Failure Mode
Detection and Countermeasure sequence
Write
Erase failure
Program failure
Read Status after Erase Block Replacement
Read Status after Program Block Replacement
Read
Up to 4 bits failure Verify ECC ECC Correction
Note: Error Correcting Code --> RS Code or BCH Code etc.
Example: 4bit correction / 512 Byte
Program Flow Chart
Elite Semiconductor Memory Technology Inc.
Publication Date: May 2014
Revision: 1.0
11/40

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