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PDF F59L1G81A Data sheet ( Hoja de datos )

Número de pieza F59L1G81A
Descripción 1 Gbit (128M x 8) 3.3V NAND Flash Memory
Fabricantes Elite Semiconductor 
Logotipo Elite Semiconductor Logotipo



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ESMT
Flash
FEATURES
z Voltage Supply: 2.6V ~ 3.6V
z Organization
- Memory Cell Array: (128M + 4M) x 8bit
- Data Register: (2K + 64) x 8bit
z Automatic Program and Erase
- Page Program: (2K + 64) bytes
- Block Erase: (128K + 4K) bytes
z Page Read Operation
- Page Size: (2K + 64) bytes
- Random Read: 25us (Max.)
- Serial Access: 25ns (Min.)
z Memory Cell: 1bit/Memory Cell
z Fast Write Cycle Time
- Program time: 200us (Typ.)
- Block Erase time: 1.5ms (Typ.)
z Command/Address/Data Multiplexed I/O Port
z Hardware Data Protection
- Program/Erase Lockout During Power Transitions
z Reliable CMOS Floating Gate Technology
z Endurance:
- 100K Program/Erase Cycles (with 1 bit/528 bytes ECC)
- Data Retention: 10 Years
z Command Driven Operation
z Cache Program Operation for High Performance Program
z Copy-Back Operation
z No Bad-Block-Erasing-Protect function (user should manage
bad blocks before erasing)
F59L1G81A
1 Gbit (128M x 8)
3.3V NAND Flash Memory
ORDERING INFORMATION
Product ID
Speed
Package
F59L1G81A -25TG
25 ns
48 pin TSOPI
F59L1G81A -25BG
25 ns
63 ball BGA
Comments
Pb-free
Pb-free
GENERAL DESCRIPTION
Offered in 128Mx8 bits, this device is 1Gbit with spare 32Mbit
capacity. The device is offered in 3.3V VCC. Its NAND cell
provides the most cost effective solution for the solid state mass
storage market. A program operation can be performed in typical
200us on the 2,112-byte page and an erase operation can be
performed in typical 1.5ms on a (128K+4K) bytes block. Data in
the data register can be read out at 25ns cycle time per byte.
The I/O pins serve as the ports for address and data input/output
as well as command input. The on-chip write controller
automates all program and erase functions including pulse
repetition, where required, and internal verification and
margining of data. Even the write-intensive systems can take
advantage of this device’s extended reliability of 100K
program/erase cycles by providing ECC (Error Correcting Code)
with real time mapping-out algorithm.
This device is an optimum solution for large nonvolatile storage
applications such as solid state file storage and other portable
applications requiring non-volatility.
Elite Semiconductor Memory Technology Inc.
Publication Date: Oct. 2013
Revision: 1.2
1/35

1 page




F59L1G81A pdf
ESMT
F59L1G81A
Product Introduction
This device is a 1,056Mbits (1,107,296,256 bits) memory organized as 65,539 rows (pages) by 2,112-byte columns. Spare 64-byte
columns are located from column address of 2,048 to 2,111.
A 2,112-byte data register and 2,112-byte cache register are serially connected to each other. Those serially connected registers are
connected to memory cell arrays for accommodating data transfer between the I/O buffers and memory cells during page read and
page program operations. The memory array is made up of 32 cells that are serially connected to form a NAND structure. Each of the
32 cells resides in a different page. A block consists of two NAND structured strings. A NAND structure consists of 32 cells. Total
1,081,344 NAND cells reside in a block. The program and read operations are executed on a page basis, while the erase operation is
executed on a block basis. The memory array consists of 1,024 separately erasable 128K-byte blocks. It indicates that the bit by bit
erase operation is prohibited on the device.
This device uses addresses multiplexed scheme. This scheme dramatically reduces pin counts and allows systems upgrades to future
densities by maintaining consistency in system board design. Command, address and data are all written through I/O's by bringing
WE to low while CE is low. Those are latched on the rising edge of WE . Command Latch Enable (CLE) and Address Latch
Enable (ALE) are used to multiplex command and address respectively, via the I/O pins. Some commands require one bus cycle. For
example, Reset Command, Status Read Command, etc require just one cycle bus. Some other commands, like page read and block
erase and page program, require two cycles: one cycle for setup and the other cycle for execution. The total physical space requires 28
addresses, thereby requiring four cycles for addressing: 2 cycle of column address, 2 cycles of row address, in that order. Page Read
and Page Program need the same four address cycles following the required command input. In Block Erase operation, however, only
the 2 cycles of row address are used. Device operations are selected by writing specific commands into the command register. Below
table defines the specific commands of this device.
The device provides cache program in a block. It is possible to write data into the cache registers while data stored in data registers are
being programmed into memory cells in cache program mode. The program performance may be dramatically improved by cache
program when there are lots of pages of data to be programmed.
In addition to the enhanced architecture and interface, the device incorporates copy-back program feature from one page to another
page without need for transporting the data to and from the external buffer memory. Since the time-consuming serial access and
data-input cycles are removed, system performance for solid-state disk application is significantly increased.
Command Set
Function
1st Cycle
2nd Cycle
Read
00h 30h
Read for Copy Back
00h 35h
Read ID
90h -
Reset
FFh -
Page Program
80h 10h
Cache Program
80h 15h
Copy-Back Program
85h 10h
Block Erase
Random Data Input(1)
Random Data Output(1)
60h
85h
05h
D0h
-
E0h
Read Status
70h -
Note:
1. Random Data Input / Output can be executed in a page.
Acceptable Command
during Busy
O
O
Caution: Any undefined command inputs are prohibited except for above command set of above table.
Elite Semiconductor Memory Technology Inc.
Publication Date: Oct. 2013
Revision: 1.2
5/35

5 Page





F59L1G81A arduino
ESMT
Read Flow Chart
START
CMD 00h
Write Address
CMD 30h
Read Data
Reclaim the
Error
No
Verify ECC
Yes
Page Read
Completed
F59L1G81A
Elite Semiconductor Memory Technology Inc.
Publication Date: Oct. 2013
Revision: 1.2
11/35

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