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PDF FAN6757 Data sheet ( Hoja de datos )
| Número de pieza | FAN6757 | |
| Descripción | PWM Controller | |
| Fabricantes | Fairchild Semiconductor | |
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FAN6757— mWSaver® PWM Controller
November 2013
Features
Single-Ended Topologies, such as Flyback and
Forward Converters
mWSaver® Technology
- Achieves Low No-Load Power Consumption:
<50 mW at 230 VAC (EMI Filter Loss Included)
- Eliminates X Capacitor Discharge Resistor Loss
with AX-CAP® Technology
- Linearly Decreases Switching Frequency
to 23 kHz
- Burst Mode Operation at Light-Load Condition
- 500 V High-Voltage JFET Startup Circuit to
Eliminate Startup Resistor Loss
Highly Integrated with Rich Features
- Proprietary Frequency Hopping to Reduce EMI
- High-Voltage Sampling to Detect Input Voltage
- Peak-Current-Mode Control with Slope
Compensation
- Cycle-by-Cycle Current Limiting with Line
Compensation
- Leading-Edge Blanking (LEB)
- Built-In 7 ms Soft-Start
Advanced Protections
- Brown-In/Brownout Recovery
- Internal Overload / Open-Loop Protection (OLP)
- VDD Under-Voltage Lockout (UVLO)
- VDD Over-Voltage Protection (VDD OVP)
- Over-Temperature Protection (OTP)
- Current-Sense Short-Circuit Protection (SSCP)
Description
The FAN6757 is a next-generation Green Mode PWM
controller with innovative mWSaver® technology, which
dramatically reduces standby and no-load power
consumption, enabling conformance to worldwide
Standby Mode efficiency guidelines.
An innovative AX-CAP® method minimizes losses in the
EMI filter stage by eliminating X-cap discharge resistors
while meeting IEC61010-1 safety requirements.
Protections ensure safe operation of the power system
in various abnormal conditions. A proprietary frequency-
hopping function decreases EMI emission. Built-in
synchronized slope compensation allows more stable
Peak-Current-Mode control over a wide range of input
voltage and load conditions. The proprietary internal line
compensation ensures constant output power limit over
the entire universal line voltage range.
Requiring a minimum number of external components,
FAN6757 provides a basic platform that is well suited for
cost-effective flyback converter designs that require
extremely low standby power consumption.
Applications
Flyback power supplies that demand extremely low
standby power consumption, such as:
Adapters for Notebooks, Printers, Game Consoles
Open-Frame SMPS for LCD TV, LCD Monitors,
Printers
Ordering Information
Part Number
Protections(1)
OLP OVP OTP SSCP
Operating
Temperature Range
FAN6757MRMX A/R
L
L A/R
-40 to +105°C
Note:
1. A/R = Auto Recovery Mode protection, L = Latch Mode protection.
Package
8-Pin, Small-Outline
Package (SOP)
Packing
Method
Tape &
Reel
© 2013 Fairchild Semiconductor Corporation
FAN6757 • Rev. 1.0.1
www.fairchildsemi.com
1 page  
Electrical Characteristics
VDD=15 V and TJ=TA=25C unless otherwise noted.
Symbol
Parameter
Conditions
VDD Section
VDD-ON Threshold Voltage to Startup
VDD Rising
VUVLO
Threshold Voltage to Stop Switching in
Normal Mode
VDD Falling
VRESTART
Threshold Voltage to enable HV Startup
to Charge VDD in Normal Mode
VDD Falling
VDD-OFF
Threshold Voltage to Stop Operating in
Protection Mode
VDD Falling
VDD-OLP
Threshold Voltage to Enable HV Startup
to Charge VDD in Protection Mode
VDD Falling
VDD-LH
Threshold Voltage to Release Latch
Mode
VDD Falling
VDD-AC
IDD-ST
IDD-OP1
Minimum Voltage of VDD Pin for
Enabling Brown-in to Avoid Startup Fail
Startup Current
Supply Current in PWM Operation
VDD=VDD-ON – 0.16 V
VDD=15 V, VFB=3 V,
Gate Open
IDD-OP2 Supply Current when PWM Stops
VDD=15 V, VFB <1.4 V,
Gate Off
IDD-OLP
ILH
Internal Sink Current when VDD-
OLP<VDD<VDD-OFF in Protection Mode
Internal Sink Current when VDD<VDD-OLP
in Latch-Protection Mode
VDD = VDD-OLP + 0.1 V
VDD = 5 V
VDD-OVP
Threshold Voltage for VDD Over-Voltage
Protection
tD-VDDOVP
VDD Over-Voltage Protection Debounce
Time
HV Section
IHV
VAC-OFF
VAC-ON
△VAC
tD-AC-OFF
tS-WORK
Inherent Current Limit of HV Pin
Threshold Voltage for Brownout
Threshold Voltage for Brown-In
VAC-ON – VAC-OFF
Debounce Time for Brownout
Work Period of HV-Sampling Circuit in
Standby Mode
VAC=90 V (VDC=120 V),
VDD=0 V
DC Source Series,
R=200 kΩ to HV Pin
DC Source Series,
R=200 kΩ to HV Pin
DC Source Series,
R=200 kΩ to HV Pin
VFB<VFB-ZDC
tS-REST
Rest Period of HV-Sampling Circuit in
Standby Mode
VFB<VFB-ZDC
VHV-DIS HV Discharge Threshold
RHV=200 kΩ to HV Pin
tD-HV-DIS
tHV-DIS
Debounce Time for HV Discharge
HV Discharge Time
© 2013 Fairchild Semiconductor Corporation
FAN6757 • Rev. 1.0.1
5
Min. Typ. Max. Unit
16 17 18 V
5.5 6.5 7.5 V
4.7 V
10 11 12 V
6 7 8V
3.5 4.0 4.5 V
VUVLO
+2.5
VUVLO
+3.0
VUVLO
+3.5
30
V
µA
1.8 mA
800 µA
90 140 190 µA
30 µA
23.5 24.5 25.5 V
110 205 300 µs
1.50 3.25 5.00 mA
90 100 110 V
100 110 120 V
8 12 16 V
40 65 90 ms
95 140 185 ms
180 260 320 ms
VDC
×0.45
75
360
VDC
×0.51
115
510
VDC
×0.56
155
660
V
ms
ms
Continued on the following page…
www.fairchildsemi.com
5 Page 
Functional Description
Current Mode Control
FAN6757 employs peak current-mode control, as shown
in Figure 21. An opto-coupler (such as the H11A817A)
and a shunt regulator (such as the KA431) are typically
used to implement the feedback network. Comparing
the feedback voltage with the voltage across the Rsense
resistor makes it possible to control the switching duty
cycle. The built-in slope compensation stabilizes the
current loop and prevents sub-harmonic oscillation.
5.4 V
ZFB
FB
2
VO
GATE
8
PWM
Comparator
Gate
driver
3R
R
SENSE
6
+
+
Slope
compensatin
KA431
Primary side
Secondary
side
Figure 21. Current Mode Control Circuit Diagram
Green-Mode Operation
The FAN6757 modulates the PWM frequency as a
function of the FB voltage to improve the medium- and
light-load efficiency, as shown in Figure 22. Since the
output power is proportional to the FB voltage in current-
mode control, the switching frequency decreases as
load decreases. In heavy-load conditions, the switching
frequency is fixed at 65 kHz. Once VFB decreases below
VFB-N (2.8 V), the PWM frequency starts linearly
decreasing from 65 kHz to 23 kHz to reduce switching
losses. As VFB drops to VFB-G (2.3 V), where switching
frequency is decreased to 23 kHz, the switching
frequency is fixed to avoid acoustic noise.
fS
fOSC
fOSC-G
VFB-ZDC VFB-ZDCR VFB-G
VFB-N
VFB
Figure 22. VFB vs. PWM Frequency
When VFB falls below VFB-ZDC (2.0 V) as load decreases
further, the FAN6757 enters Burst Mode operation,
where PWM switching is disabled. Then the output
voltage starts to drop, causing the feedback voltage to
rise. Once VFB rises above VFB-ZDCR (2.1 V), switching
resumes. Burst Mode alternately enables and disables
switching, reducing switching loss for lower power
consumption, as shown in Figure 23.
VO
VFB
VVFFBB..ZZDDCCR
IDrain
Switching
Disabled
Switching
Disabled
Figure 23. Burst Switching in Green Mode
Operating Current
In normal conditions, operating current is less than
1.8 mA (IDD-OP1). When VFB<1.4 V, operating current is
further reduced below 800 µA (IDD-OP2) by disabling
several blocks of the FAN6757. The low operating
current improves light-load efficiency and reduces the
requirement of VDD hold-up capacitance.
High-Voltage Startup and Line Sensing
The HV pin is typically connected to the AC line input
through two external diodes and one resistor (RHV), as
shown in Figure 24. When the AC line voltage is
applied, the VDD hold-up capacitor is charged by the line
voltage through the diodes and resistor. After VDD
reaches the turn-on threshold voltage (VDD-ON), the
startup circuit charging VDD capacitor is switched off and
VDD is supplied by the auxiliary winding of the
transformer. Once the FAN6757 starts up, it continues
operation until VDD drops below 6.5 V (VUVLO). The IC
startup time with a given AC line input voltage is:
tSTARTUP
RHV
VACIN
CDD
ln
VAC IN
22
22
VDD ON
(1)
RHV
CX
AC Line
HV
4
VDD
Good
RLS
Sampling
Circuit
VDD-ON/
VRESTART
7
VDD
CDD
Brown-in/out
Function
High/ Low Line
Compensation
VLIMIT
VOCP
Figure 24. Startup Circuit
© 2013 Fairchild Semiconductor Corporation
FAN6757 • Rev. 1.0.1
11
www.fairchildsemi.com
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet FAN6757.PDF ] | |
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