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PDF F1C100 Data sheet ( Hoja de datos )

Número de pieza F1C100
Descripción Processer
Fabricantes Allwinner 
Logotipo Allwinner Logotipo



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No Preview Available ! F1C100 Hoja de datos, Descripción, Manual

Allwinner
F1C100 Datasheet
F1C100 Processer
Datasheet
V1.0
2011-3-31
F1C100 datasheet 属于珠海全志科技有限公司之商业机密;除非珠海全志科技有限公司授权,任何机构
和个人对本 F1C100 之全部或部分内容不得有复制、复印或向第三方传播之行为;珠海全志科技有限公司保
留一切法律之权利.

1 page




F1C100 pdf
Allwinner
F1C100 Datasheet
2 Description
The F1C100 processor is a highly integrated programmable platform for Media Application.
The F1C100 processor contains a rich set of peripherals connected to the ARM926-EJS via several
high bandwidth buses, providing flexibility in system configuration as well as excellent overall
system performance. The general-purpose peripherals include functions such as USB HS/FS DRD,
UART, SPI, TWI, LCD controller, TV encoder, SD/MMC I/F, SDRAM I/F, a watchdog timer. This
set of functions satisfies a wide variety of typical system support needs and is augmented by the
system expansion capabilities of the part. In addition to these general-purpose peripherals, the
processor contains high speed serial and parallel ports for interfacing to a variety of audio and
video function.
3 Feature
The systems include the following feature:
ARM926-EJS 16KB I-Cache/16KB D-Cache
Support 16 bits SDR
Two 32-bit Programmed Timers
Enhanced 8-CH Direct-Memory-Access Controller
Built in Pulse Width Modulator
Built in USB 2.0 HS
Built in Touch Panel Interface
Built in Low Resolution A/D convertor
On-chip Sigma-Delta A/D with SNR up to 95dBA-Weight
On-chip Sigma-Delta D/A and PA with SNR up to 100dBA-Weight
On-Chip ROM Boot loader
Built in HDTV encoder
Built in LCD controller
Built in IrDA for remote control
Built in audio codec for headphone and microphone application
Support SLC/MLC NAND flash up to 64bits ECC
Support SD/TF/MMC card
Fully support PMU application
Video Decoder Engine(all format up to 1280*720@30fps)
H.264
Fully compatible with ISO-14496-10 in BP/MP/HP
Supports CABAC/CAVLC
Supports frame/field/MAFF structure
Variable block size(16x16, 16x8, 8x16, 8x8, 8x4, 4x8 and 4x4)
MPEG-1
Fully compatible with ISO/IEC 11172-2 Mpeg1 specification
F1C100 datasheet 属于珠海全志科技有限公司之商业机密;除非珠海全志科技有限公司授权,任何机构和
个人对本 F1C100 之全部或部分内容不得有复制、复印或向第三方传播之行为;珠海全志科技有限公司保留一
切法律之权利.

5 Page





F1C100 arduino
Allwinner
F1C100 Datasheet
30
LCDD15
I/O
LCD Data Bus Bit 15
32
LCDD18
I/O
LCD Data Bus Bit 18
33
LCDD19
I/O
LCD Data Bus Bit 19
34
LCDD20
I/O
LCD Data Bus Bit 20
35
LCDD21
I/O
LCD Data Bus Bit 21
36
LCDD22
I/O
LCD Data Bus Bit 22
37
LCDD23
I/O
LCD Data Bus Bit 23
41 LCDCLK I/O pull-up LCD Clock
38
LCDDE
I/O pull-down
LCD Data Enable
39
LCDHSYNC I/O pull-down
LCD Horizon Sync
40
LCDVSYNC I/O pull-down
LCD Vertical Sync
6.4 USB Interface Pin
Pin Num
70
71
69
Pin Name
USBDM
USBDP
UVCC
Type Default Status Description
USB DM signal
USB DP signal
USB 3.3V power
6.5 Touch Panel Interface Pin
Pin Num
60
61
62
63
Pin Name
X1
X2
Y1
Y2
Type Default Status Description
Touch Panel X1 input
Touch Panel X2 input
Touch Panel Y1 input
Touch Panel Y1 input
6.6 Audio Codec Interface Pin
Pin Num
46
50
49
48
47
57
58
Pin Name Type Default Status
HPL
HPR
HPCOM
HPCOM-FB
HPVCC
FMINL
FMINR
Description
Headphone Left Channel Output
Headphone Right Channel Output
Headphone Common Mode
Headphone Common Mode Feedback
Headphone 3.0V power bypass
Line Input Left Channel
Line Input Right Channel
F1C100 datasheet 属于珠海全志科技有限公司之商业机密;除非珠海全志科技有限公司授权,任何机构和
个人对本 F1C100 之全部或部分内容不得有复制、复印或向第三方传播之行为;珠海全志科技有限公司保留一
切法律之权利.

11 Page







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