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PDF TDA21320 Data sheet ( Hoja de datos )
| Número de pieza | TDA21320 | |
| Descripción | High-Performance DrBLADE | |
| Fabricantes | Infineon | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de TDA21320 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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High-Performance DrBLADE
6.6 mm x 4.5 mm x 0.6 mm
TDA21320
Data Sheet
Revision 2.4, 2015-07-16
Power Management and Multi Market
1 page  
3 Description
3.1 Pinout
TDA21320
Description
Figure 2 Pinout, Numbering and Name of Pins (transparent top view)
Table 2
Pin No.
2
3
4
5
7
8
9
33-38
(pads)
I/O Signals
Name
PWM
OFF#
IMON
IMONREF
TMON/FAULT
BOOT
PHASE
SW
Pin Type Buffer Type Function
I/O +3.3 V logic PWM drive logic input, Status output for VCIN
The tri-state PWM input is compatible with 3.3 V.
I +3.3 V logic Deactivates LS-MOSFET
Pull low to prevent LS-FET turn-on. Leave open if not used.
(If traced out in noisy layout it may require external pull up.)
O
Analog
Load current Sensing
Provides a voltage proportional to the high/low-side
MOSFET currents; Leave open if not used.
O
Analog
Load current Sensing
Reference to pin 4; Leave open if not used.
O
Analog/
Thermal Sensing / Fault Pin
Digital
Temperature reporting, fault signaling by logic “H”; Status
output of VDRV, Leave open if not used.
I
Analog
Bootstrap voltage pin
Connect to BOOT capacitor
I
Analog
Switch node input
Internally connected to SW pins, Connect to BOOT
capacitor as reference pin for boot voltage
O
Analog
Switch node output
High current output switching node
Data Sheet
5 Revision 2.4, 2015-07-16
5 Page 
TDA21320
Electrical Specification
Table 9
Voltage Supply And Biasing Current
Parameter Symbol
Values
Unit Note / Test Condition
UVLO VCIN
rising
VUVLO1_R
Min. Typ. Max.
3.0 – 4.0 V
UVLO VCIN VUVLO1_F
falling
2.6 – 3.6
Driver enable threshold; above threshold driver is active,
driver responds to PWM input when UVLO VDRV and
UVLO BOOT are enabled, TMON/FAULT reports driver
temperature when UVLO VDRV is enabled
Driver disable threshold; below threshold driver is inactive,
PWM and TMON/FAULT held low by pull-down resistors
UVLO VDRV VUVLO2_R
rising
4.16 4.25 4.34 V
GL, GH and TMON/FAULT enable threshold; when UVLO
VCIN is enabled then: above threshold GL is enabled, GH
depends on UVLO BOOT, TMON/FAULT is released to
report driver temperature
UVLO VDRV VUVLO2_F
falling
3.7 3.8 3.9
GL, GH and TMON/FAULT disable threshold; when UVLO
VCIN is enabled: below threshold after 3 consecutive cycles
or 15 µs (typ.) the driver outputs GL/GH are disabled,
TMON/FAULT stops temperature reporting and is held low
by pull-down resistor
UVLO BOOT VUVLOboot_R 3.88 4.05 4.22 V
rising
UVLO BOOT VUVLOboot_F 3.5 3.63 3.76
falling
Driver current IVDRV_600kHz – 27 – mA
IVDRV_1MHz
– 44
–
IC current
(control)
IVCIN_O
– 1.0 – mA
IC quiescent ICIN+IDRV
– 1.2 –
Pre-Bias at
SW
VSW_0
– 120 160 mV
VBOOT-VSW rising, GH enable threshold; when UVLO VCIN
and UVLO VDRV are active: above threshold GH responds
to PWM
VBOOT-VSW falling, GL/GH disable threshold; when UVLO
VCIN and UVLO VDRV are enabled: below threshold
counter starts, after 3 consecutive PWM cycles driver
outputs are disabled
OFF# = 3.3 V, fSW = 600 kHz
OFF# = 3.3 V, fSW = 1 MHz
OFF# = 3.3 V, PWM = Open for > 19 µs (typ.)
PWM in Tri-state (VPWM_S), VCIN = VDRV = 5V, internal pull-
down resistor 1.5 kΩ
Data Sheet
11 Revision 2.4, 2015-07-16
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet TDA21320.PDF ] | |
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