PDF LC75812PT Datasheet ( Hoja de datos )

		

1 Page



(1) When CL is stopped at the low level
CE
VIH1
CL 50%
VIL1
DI VIH1
VIL1
DO
tds
tφH
tdh
tφL
LC75812PT
VIH1
tcp tcs
D0
(2) When CL is stopped at the high level
[Figure 2]
tdc
VIL1
tch
D1
tdr
VIH1
CE
tφL tφH VIH1
CL 50%
VIL1
tcp tcs
DI
VIH1
VIL1
tds tdh
DO D0
[Figure 3]
(3) OSC pin clock timing in external clock operating mode
D1
tdc
OSC
VIH2
50%
VIL2
tCKH
tCKL
[Figure 4]
fCK=
1
tCKH + tCKL
[kHz]
DCK=
tCKH
tCKH + tCKL
×100[%]
VIL1
tch
tdr
No.A1417-5/54

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Serial Data Input
(1) When CL is stopped at the low level
LC75812PT
CE
CL
DI 0 1 0 0 0 0 1 0 D0 D1 D2 D3 D4
D118 D119
B0 B1 B2 B3 A0 A1 A2 A3
Instruction data (Up to 120 bits)
DO
(2) When CL is stopped at the high level
CE
CL
DI 0 1 0 0 0 0 1 0 D0 D1 D2 D3 D4
D118 D119
B0 B1 B2 B3 A0 A1 A2 A3
Instruction data (Up to 120 bits)
DO
• B0 to B3, A0 to A3: CCB address 42H
• D0 to D119: Instruction data
The data is acquired on the rising edge of the CL signal and latched on the falling edge of the CE signal. When
transferring instruction data from the microcontroller, applications must assure that the time from the transfer of one set
of instruction data until the next instruction data transfer is significantly longer than the instruction execution time.
No.A1417-11/54

 11 Page