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PDF CAT34TS00 Data sheet ( Hoja de datos )

Número de pieza CAT34TS00
Descripción 1.8V Digital Temperature Sensor
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CAT34TS00
1.8 V Digital Temperature
Sensor
Description
CAT34TS00 is a low-voltage digital temperature sensor, which
implements the JEDEC JC42.4 specification. CAT34TS00 measures
temperature every 100 ms over a range of −20°C to +125°C, with a
resolution of 12 bits.
The host communicates with the device via the serial I2C / SMBus
Interface, at either 100 kHz or 400 kHz. Temperature readings can be
retrieved via serial interface. Internally, they are compared to high,
low and critical trigger limits stored in device registers. Over or under
limit conditions can be signaled on the open−drain EVENT pin. These
limits, as well as other settings, can be configured via serial interface.
Features
JEDEC JC42.4 Compliant Temperature Sensor
Supply Range: 1.7 V to 1.9 V
Temperature Range: −20°C to +125°C
I2C / SMBus Interface
Temperature Sampling Rate: 100 ms max
Temperature Reading Accuracy:
±0.5°C typ for Active Range (+75°C to +95°C)
Schmitt Triggers and Noise Suppression Filters on SCL and SDA
Inputs
2 x 3 x 0.75 mm TDFN Package
These Devices are Pb−Free and are RoHS Compliant
Typical Applications
Solid State Drives
Graphics Cards
Portable Devices
Process Control Equipment
VCC
SCL
A2, A1, A0
SDA
CAT34TS00
EVENT
VSS
Figure 1. Functional Symbol
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TDFN−8
VP2 SUFFIX
CASE 511AK
PIN CONFIGURATION
A0 1
A1
(Top View)
A2
VSS
VCC
EVENT
SCL
SDA
TDFN (VP2)
For the location of Pin 1, please consult the
corresponding package drawing.
MARKING DIAGRAM
TDFN−8
OTA
ALL
YM
G
OTA = Specific Device Code
A = Assembly Location Code
LL = Assembly Lot Number (Last Two Digits)
Y = Production Year (Last Digit)
M = Production Month (1 − 9, O, N, D)
G = Pb−Free Package
= Pin 1 Indicator
PIN FUNCTIONS
Pin Name
Function
A0, A1, A2
VSS
SDA
SCL
Device Address Inputs
Ground
Serial Data Input / Output
Serial Clock Input
EVENT
Open−drain Event Output
VCC
DAP
Ground
Backside Exposed DAP at VSS
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 14 of this data sheet.
© Semiconductor Components Industries, LLC, 2014
July, 2014 − Rev. 0
1
Publication Order Number:
CAT34TS00/D

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CAT34TS00 pdf
CAT34TS00
Pin Description
SCL: The Serial Clock input pin accepts the Serial Clock
generated by the Master (Host).
SDA: The Serial Data I/O pin receives input data and transmits
data stored in the TS registers. In transmit mode, this pin is
open drain. Data is acquired on the positive edge, and is
delivered on the negative edge of SCL.
A0, A1 and A2: The Address pins accept the device address.
These pins have on−chip pull−down resistors.
EVENT: The open−drain EVENT pin can be programmed
to signal over/under temperature limit conditions.
Power−On Reset (POR)
The CAT34TS00 incorporates Power−On Reset (POR)
circuitry which protects the device against powering up to an
undetermined logic state. As VCC exceeds the POR trigger
level, the device will power up into conversion mode. When
VCC drops below the POR trigger level, the device will
power down into Reset mode.
This bi−directional POR behavior protects CAT34TS00
against brown−out failure following a temporary loss of
power. The POR trigger level is set below the minimum
operating VCC level.
Device Interface
The CAT34TS00 supports the Inter−Integrated Circuit
(I2C) and the System Management Bus (SMBus) data
transmission protocols. These protocols describe serial
communication between transmitters and receivers sharing a
2−wire data bus. Data flow is controlled by a Master device,
which generates the serial clock and the START and STOP
conditions. The CAT34TS00 acts as a Slave device. Master
and Slave alternate as transmitter and receiver. Up to 8
CAT34TS00 devices may be present on the bus
simultaneously, and can be individually addressed by
matching the logic state of the address inputs A0, A1, and A2.
The CAT34TS00 contains eight 16−bit internal registers
which can be accessed for write and read using the
I2C/SMBus protocol.
I2C/SMBus Protocol
The I2C/SMBus uses two ‘wires’, one for clock (SCL) and
one for data (SDA). The two wires are connected to the VCC
supply via pull−up resistors. Master and Slave devices
connect to the bus via their respective SCL and SDA pins.
The transmitting device pulls down the SDA line to
‘transmit’ a ‘0’ and releases it to ‘transmit’ a ‘1’.
Data transfer may be initiated only when the bus is not
busy (see A.C. Characteristics).
During data transfer, the SDA line must remain stable
while the SCL line is HIGH. An SDA transition while SCL
is HIGH will be interpreted as a START or STOP condition
(Figure 3).
START
The START condition precedes all commands. It consists
of a HIGH to LOW transition on SDA while SCL is HIGH.
The START acts as a ‘wake−up’ call to all Slaves. Absent a
START, a Slave will not respond to commands.
STOP
The STOP condition completes all commands. It consists
of a LOW to HIGH transition on SDA while SCL is HIGH.
The STOP tells the Slave that no more data will be written
to or read from the Slave.
Device Addressing
The Master initiates data transfer by creating a START
condition on the bus. The Master then broadcasts an 8−bit
serial Slave address. The first 4 bits of the Slave address (the
preamble) are fixed at binary 0011 (3hex). The next 3 bits,
A2, A1 and A0, select one of 8 possible Slave devices. The
last bit, R/W, specifies whether a Read (1) or Write (0)
operation is being performed.
Acknowledge
A matching Slave address is acknowledged (ACK) by the
Slave by pulling down the SDA line during the 9th clock
cycle (Figure 4). After that, the Slave will acknowledge all
data bytes sent to the bus by the Master. When the Slave is
the transmitter, the Master will in turn acknowledge data
bytes in the 9th clock cycle. The Slave will stop transmitting
after the Master does not respond with acknowledge
(NoACK) and then issues a STOP. Bus timing is illustrated
in Figure 5.
SDA
SCL
START BIT
Figure 3. Start/Stop Timing
STOP BIT
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CAT34TS00 arduino
CAT34TS00
Register Data Format
The values used in the temperature data register and the 3
temperature trip point registers are expressed in two’s
complement format. The measured temperature value is
expressed with 12−bit resolution, while the 3 trip
temperature limits are set with 10−bit resolution. The total
temperature range is arbitrarily defined as 256°C, thus
yielding an LSB of 0.0625°C for the measured temperature
and 0.25°C for the 3 limit values. Bit B12 in all temperature
registers represents the sign, with a ‘0’ indicating a positive,
and a ‘1’ a negative value. In two’s complement format,
negative values are obtained by complementing their
positive counterpart and adding a ‘1’, so that the sum of
opposite signed numbers, but of equal absolute value, adds
up to zero.
Note that trailing ‘0’ bits, are ‘0’ irrespective of polarity.
Therefore the “don’t care” bits (B1 and B0) in the 10−bit
resolution temperature limit registers, are always ‘0’.
Table 14. 12−BIT TEMPERATURE DATA FORMAT
Binary (B12 to B0)
Hex Temperature
1 1100 1001 0000
1C90
−55°C
1 1100 1110 0000
1CE0
−50°C
1 1110 0111 0000
1E70
−25°C
1 1111 1111 1111
1FFF
−0.0625°C
0 0000 0000 0000
000
0°C
0 0000 0000 0001
001 +0.0625°C
0 0001 1001 0000
190
+25°C
0 0011 0010 0000
320
+50°C
0 0111 1101 0000 7D0 +125°C
Event Pin Functionality
The EVENT output reacts to temperature changes as
illustrated in Figure 9, and according to the operating mode
defined by the Configuration register.
In Interrupt Mode, the (enabled) EVENT output will be
asserted every time the temperature crosses one of the alarm
window limits, and can be de−asserted by writing a ‘1’ to the
clear event bit (B5) in the configuration register. Once the
temperature exceeds the critical limit, the EVENT remains
asserted as long as the temperature stays above the critical
limit and cannot be cleared. A clear request sent to the
CAT34TS00 while the temperature is above the critical limit
will be acknowledged, but will be executed only after the
temperature drops below the critical limit.
In Comparator Mode, the EVENT output is asserted
outside the alarm window limits, while in Critical
Temperature Mode, EVENT is asserted only above the
critical limit. Clear requests are ignored in this mode. The
exact trip limits are determined by the 3 temperature limit
settings and the hysteresis offsets, as illustrated in Figure 10.
Following a TS shut−down request, the converter is
stopped and the most recently recorded temperature value
present in the TDR is frozen; the EVENT output will continue
to reflect the state immediately preceding the shut−down
command. Therefore, if the state of the EVENT output
creates an undesirable bus condition, appropriate action must
be taken either before or after shutting down the TS. This may
require clearing the event, disabling the EVENT output or
perhaps changing the EVENT output polarity.
In normal use, events are triggered by a change in
recorded temperature, but the CAT34TS00 will also respond
to limit register changes. Whereas recorded temperature
values are updated at sampling rate frequency, limits can be
modified at any time. The enabled EVENT output will react
to limit changes as soon as the respective registers are
updated. This feature may be useful during testing.
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