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PDF S3921 Data sheet ( Hoja de datos )

Número de pieza S3921
Descripción NMOS linear image sensor
Fabricantes Hamamatsu Corporation 
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IMAGE SENSOR
NMOS linear image sensor
S3921/S3924 series
Voltage output type with current-integration readout circuit and impedance conversion circuit
NMOS linear image sensors are self-scanning photodiode arrays designed specifically as detectors for multichannel spectroscopy. The scanning
circuit is made up of N-channel MOS transistors, operates at low power consumption and is easy to handle. Each photodiode has a large active
area, high UV sensitivity yet very low noise, delivering a high S/N even at low light levels. NMOS linear image sensors also offer excellent output
linearity and wide dynamic range.
S3921/S3924 series have a current-integration readout circuit utilizing the video line and an impedance conversion circuit. The output is available
in boxcar waveform allowing signal readout with a simple external circuit.
The photodiodes of S3921 series have a height of 2.5 mm and are arrayed in a row at a spacing of 50 µm. The photodiodes of S3924 series also
have a height of 2.5 mm but are arrayed at a spacing of 25 µm. The photodiodes are available in 3 different pixel quantities for each series, 128
(S3921-128Q), 256 (S3921-256Q, S3924-256Q) and 512 (S3921-512Q, S3924-512Q) and 1024 (S3924-1024Q). Quartz glass is the standard
window material.
Features
Applications
Built-in current-integration readout circuit utilizing
Multichannel spectrophotometry
video line capacitance and impedance conversion
circuit (boxcar waveform output)
Image readout system
Wide active area
Pixel pitch: 50 µm (S3921 series)
25 µm (S3924 series)
Pixel height: 2.5 mm
High UV sensitivity with good stability
Low dark current and high saturation charge allow a long
integration time and a wide dynamic range at room temperature
Excellent output linearity and sensitivity spatial uniformity
Low voltage, single power supply operation
Start pulse, clock pulse and video line reset pulse are
CMOS logic compatible
Equivalent circuit
Active area structure
Start
Clock
Clock
st
1
2
Address
switch
Active
photodiode
Saturation
control gate
Saturation
control drain
Address
switch
Dummy diode
Digital shift register
(MOS shift register)
End of scan
Source follower circuit
Vdd
Active video
Vss
Dummy video
Reset switch
Reset
Reset V
b
a
Oxidation silicon
N type silicon
KMPDC0019EA
P type silicon
Absolute maximum ratings
Parameter
Supply voltage
Input pulse (φ1, φ2, φst) voltage
Power consumption*1
Operating temperature*2
Storage temperature
*1: Vdd=5 V, Vr=2.5 V
*2: No condensation
Symbol
Vdd
Vφ
P
Topr
Tstg
S3921 series: a=50 µm, b=45 µm
S3924 series: a=25 µm, b=20 µm
Value
15
15
10
-40 to +65
-40 to +85
KMPDA0067EA
Unit
V
V
mW
°C
°C
1

1 page




S3921 pdf
NMOS linear image sensor S3921/S3924 series
Active area structure” shows the schematic diagram of the
photodiode active area. This active area has a PN junction
consisting of an N-type diffusion layer formed on a P-type
silicon substrate.
A signal charge generated by light input accumulates as a
capacitive charge in this PN junction. The N-type diffusion
layer provides high UV sensitivity but low dark current.
Driver circuit
A start pulse φst and 2-phase clock pulses φ1, φ2 are needed
to drive the shift register. These start and clock pulses are
positive going pulses and CMOS logic compatible.
The 2-phase clock pulses φ1, φ2 can be either completely
separated or complementary. However, both pulses must not
be “High” at the same time.
A clock pulse space (X1 and X2 in “Timing chart for driver
circuit”) of a “rise time/fall time - 20” ns or more should be
input if the rise and fall times of φ1, φ2 are longer than 20 ns.
The φ1 and φ2 clock pulses must be held at “High” at least
Timing chart for driver circuit
st
V s (H)
V s (L)
1
V 1 (H)
V 1 (L)
2
V 2 (H)
V 2 (L)
Vr (H)
Reset Vr (L)
Active video output
End of scan
tpw s
tpw 1
tpw 2
tvd
st
1
2
Reset
tr s tf s
tr 1 tf 1
X1 X2 tf 2
t ov
ts r-2
t ovr td r-2
tfr trr
200 ns. Since the photodiode signal is obtained at the rise of
each φ2 pulse, the clock pulse frequency will equal the video
data rate.
The amplitude of start pulse φst is the same as the φ1 and φ2
pulses. The shift register starts the scanning at the “High”
level of φst, so the start pulse interval is equal to signal accu-
mulation time. The φst pulse must be held “High” at least 200
ns and overlap with φ2 at least for 200 ns. To operate the shift
register correctly, φ2 must change from the “High” level to the
“Low” level only once during “High” level of φst. The timing
chart for each pulse is shown in “Timing chart for driver
circuit”.
End of scan
The end of scan (EOS) signal appears in synchronization
with the φ2 timing right after the last photodiode is addressed,
and the EOS terminal should be pulled up at 5 V using a 10
kΩ resistor.
Reset V voltage margin
12
10
8
6
Recommended
reset
V
voltage
Max.
4 Reset V voltage range
2
Min.
0
4 5 6 7 8 9 10
Clock pulse amplitude (V)
KMPDB0047EA
KMPDC0026EA
Signal readout circuit
S3921/S3924 series include a current integration circuit uti-
lizing the video line capacitance and an impedance conver-
sion circuit. This allows signal readout with a simple external
circuit. However, a positive bias must be applied to the video
line because the photodiode anode of NMOS linear image
sensors is at 0 V (Vss). This is done by adding an appropriate
pulse to the reset φ terminal. The amplitude of the reset pulse
should be equal to φ1, φ2 and φst.
When the reset pulse is at the high level, the video line is set
at the Reset V voltage. “Reset V voltage margin” shows the
Reset V voltage margin. A higher clock pulse amplitude al-
lows higher Reset V voltage and saturation charge. Conversely,
if the Reset V voltage is set at a low level with a higher clock
pulse amplitude, the rise and fall times of video output wave-
form can be shortened. Setting the Reset V voltage to 2.5 V is
recommended when the amplitude of φ1, φ2, φst and Reset φ
is 5 V.
To obtain a stable output, an overlap between the reset pulse
(Reset φ) and φ2 must be settled. (Reset φ must rise while φ2
is at the high level.) Furthermore, Reset φ must fall while φ2 is
at the low level.
S3921/S3924 series provide output signals with negative-
going boxcar waveform which include a DC offset of approxi-
mately 1 V when Reset V is 2.5 V. If you want to remove the DC
offset to obtain the positive-going output, the signal readout
circuit and pulse timing shown in “Readout circuit example”
and “Timing chart” are recommended. In this circuit, Rs must
be larger than 10 kΩ. Also, the gain is determined by the ratio
of Rf to Rs, so choose the Rf value that suits your application.
5

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