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Número de pieza TDA8594
Descripción 4 x 50W power amplifier
Fabricantes NXP Semiconductors 
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TDA8594
I2C-bus controlled 4 50 W power amplifier
Rev. 5 — 11 June 2013
Product data sheet
1. General description
The TDA8594 is a complementary quad Bridge Tied Load (BTL) audio power amplifier
made in BCDMOS technology. It contains four independent amplifiers in BTL
configuration. Through the I2C-bus, diagnosis of temperature warning and clipping level is
fully programmable and the information available via two diagnostic pins is selectable.
The status of each amplifier (output offset, load or no load, short-circuit or speaker
incorrectly connected) can be read separately.
2. Features and benefits
2.1 General
Operates in legacy mode (non I2C-bus) and I2C-bus mode (3.3 V and 5 V compliant)
Three hardware-programmable I2C-bus addresses
Drives 4 or 2 loads
Speaker fault detection
Independent short-circuit protection per channel
Loss of ground and open VP safe (with 200 mseries impedance and a supply
decoupling capacitor of 2200 F maximum)
All outputs short-circuit proof to ground, supply voltage and across the load
All pins short-circuit proof to ground
Temperature-controlled gain reduction to prevent audio holes at high junction
temperatures
Low battery voltage detection
Offset detection
This part has been qualified in accordance with AEC-Q100
2.2 I2C-bus mode
DC load detection: open-circuit, short-circuit and load present
AC load (tweeter) detection
During start-up, can detect which load is connected so the appropriate gain can be
selected without audio pop
Independently selectable soft mute of front channels (channel 1 and channel 3) and
rear channels (channel 2 and channel 4)
Programmable gain (26 dB and 16 dB) of front channels (channel 1 and channel 3)
and rear channels (channel 2 and channel 4)

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TDA8594 pdf
NXP Semiconductors
TDA8594
I2C-bus controlled 4 50 W power amplifier
Table 3.
Symbol
OUT1
PGND1
OUT1+
SVR
IN1
IN2
SGND
IN4
IN3
ACGND
OUT3+
PGND3
OUT3
VP1
OUT4+
SCL
OUT4
PGND4
SDA
TAB
Pin description …continued
Pin Description
8 negative channel 1 output
9 power ground channel 1
10 positive channel 1 output
11 half supply filter capacitor
12 channel 1 input
13 channel 2 input
14 signal ground
15 channel 4 input
16 channel 3 input
17 AC ground input
18 positive channel 3 output
19 power ground channel 3
20 negative channel 3 output
21 supply voltage 1
22 positive channel 4 output
23 I2C-bus clock input
24 negative channel 4 output
25 power ground channel 4
26 I2C-bus data input/output
27 heatsink connection, must be connected to ground
To keep the output pins on the front side, special reverse bending is applied.
7. Functional description
The TDA8594 is a complementary quad BTL audio power amplifier made in BCDMOS
technology. It contains four independent amplifiers in BTL configuration (see Figure 1).
Through the I2C-bus, the diagnostic functions of temperature level and clip level are fully
programmable and the information to be shown on the two diagnostic pins can be
selected. The status of each amplifier (output offset, load or no load, short-circuit or
speaker incorrectly connected) can be read separately. The TDA8594 is protected against
overvoltage, short-circuit, over-temperature, open ground and open VP connections.
Three different I2C-bus addresses are selected with an external resistor connected to the
ADSEL pin. If the ADSEL pin is short-circuit to ground, the TDA8594 operates in legacy
mode. In this mode, no I2C-bus is needed and the function of the STB pin will change from
two-level (Standby mode and On mode) to a three-level pin (Standby mode, On mode and
mute).
7.1 Input stage
The input stage is a high-impedance pseudo-differential input stage. The negative inputs
of the four channels are combined on the ACGND pin. For the best performance on
supply voltage ripple rejection and pop noise, the capacitor connected to the ACGND pin
must be four times the value of the input capacitor (or as close to the value as possible).
TDA8594
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 11 June 2013
© NXP B.V. 2013. All rights reserved.
5 of 49

5 Page





TDA8594 arduino
NXP Semiconductors
TDA8594
I2C-bus controlled 4 50 W power amplifier
VP
DIAG
on
STB mute
standby
SVR
amplifier
output
tamp_on
soft
mute
toff
fast
mute
td(mute_off)
td(soft_mute) td(mute_on)
Fig 6. Start-up and shut-down timing in legacy mode
td(fast_mute)
001aad 171
7.9 Power-on reset and supply voltage spikes
If in I2C-bus mode the supply voltage drops below 5 V (see Figure 9), the content of the
I2C-bus latches cannot be guaranteed and the power-on reset will be activated. All latches
are reset, the amplifier is switched off and the DIAG pin is pulled LOW to indicate that a
power-on reset has occurred (bit DB2[D7]). When IB1[D0] is set, the power-on flag is
reset, the DIAG pin will be released and the amplifier will start up.
In legacy mode a supply voltage drop below 5 V will switch off the amplifier and the DIAG
pin will not be pulled LOW.
7.10 Engine start and low voltage operation
The DC output voltage of the amplifier (VO) is set to half of the supply voltage and is
related to the voltage on the SVR pin (see Figure 7; VO = VSVR 1.4 V). A capacitor is
connected on the SVR pin to suppress the ripple on the power supply.
If the supply voltage drops, for instance, during an engine start, the output follows slowly
due to the SVR capacitor. The headroom voltage is the voltage needed for good operation
of the amplifier and is defined as Vhr = VP VO (see Figure 7). If the headroom voltage
becomes lower than the headroom protection threshold of 1.6 V, the headroom protection
is activated to prevent pop noise at the output. This protection first activates the fast mute
and then discharges the capacitors on the SVR and ACGND pins to generate more
headroom for the amplifier (see Figure 8).
TDA8594
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 11 June 2013
© NXP B.V. 2013. All rights reserved.
11 of 49

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