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PDF IMP3522D Data sheet ( Hoja de datos )

Número de pieza IMP3522D
Descripción ADAPTIVE BALLAST CONTROL IC
Fabricantes IMP 
Logotipo IMP Logotipo



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No Preview Available ! IMP3522D Hoja de datos, Descripción, Manual

ISO 9001 Registered
IMP3522D
ADAPTIVE BALLAST CONTROL IC
General Description
The IMP3522D(S) is a complete adaptive ballast con-
troller, 450V half-bridge driver and power MOS FET
integrated into a single IC for Compact Fluorescent
Lamps (CFL) applications. The IC includes adaptive
zero-voltage switching (ZVS), internal crest factor
over-current protection, as well as an integrated boot-
strap FET. The heart of this IC is a voltage controlled
oscillator with externally programmable minimum
frequency. All of the necessary ballast features are
integrated in a small 8-pin DIP package.
Key Features
-450V Half Bridge Driver
-Integrated Bootstrap FET
-Integrated Power MOS FET
-Adaptive zero-voltage switching (ZVS)
-Internal Crest Factor Over-Current Protection
-0 to 6VDC Voltage Controlled Oscillator
-Programmable minimum frequency
-Micropower Startup Current (80uA)
-Internal 15.6V zener clamp on VDD
-Small DIP8 Package
-Also available LEAD-FREE (PbF)
Typical Application
BR1
F1 LF
L1
CF
L2
RSUPPLY
CBUS
VDD
CVDD GND
RMIN
RRMIN VCO
CVCO
DCP2
SPIRAL
CFL
VB
VDC
OUT
CBO LRES
PGND
CDC
CSNUB
CRES
DCP1
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IMP3522D pdf
ISO 9001 Registered
IMP3522D
ADAPTIVE BALLAST CONTROL IC
Application Information
Under-voltage Lock-Out Mode
The under-voltage lock-out mode (UVLO) is defined as the state the IMP3522D is in when VDD is below the turn-on
threshold of the IC. The IMP3522D UVLO is designed to maintain an ultra-low supply current (IQDDUV<80uA), and to
guarantee that the IMP3522D is fully functional before the high- and low-side output gate drivers are activated. The VDD
capacitor, CVDD, is charged by current through supply resistor, RSUPPLY, minus the start-up current drawn by the
IMP3522D (Figure 1). This resistor is chosen to provide sufficient current to supply the IMP3522D from the DC bus.
Once the capacitor voltage on VDD reaches the start-up threshold, VDDUV+, the IMP3522D turns on and HO and LO start
oscillating. Capacitor CVDD should be large enough to hold the voltage at VDD above the VDDUV+, threshold for one half
-cycle of the line voltage or until the external auxiliary supply can maintain the required supply voltage and current to the
IC.
High-side
driver
Low-side
driver
HO
Fig. 1 Start-up circuitry
An internal bootstrap MOSFET between VDD and VB and external supply capacitor, CBO, determine the supply voltage
for the high-side driver circuitry. An external charge pump circuit consisting of capacitor CSNUB and diodes DCP1 and
DCP2, comprises the auxiliary supply voltage for the low-side driver circuitry. To guarantee that the high-side supply is
charged up before the first pulse on pin HO, the first pulse from the output drivers comes from the LO pin. LO may os-
cillate several times until VB-VOUT exceeds the high-side UVLO rising threshold, VBOUV+ (9 Volts), and the high-side
driver is enabled. During UVLO mode, the high- and low-side gate driver outputs, HO and LO, are both low and pin VCO
is pulled down to GND for resetting the starting frequency to the maximum.
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IMP3522D arduino
ISO 9001 Registered
IMP3522D
ADAPTIVE BALLAST CONTROL IC
Application Information (Continued)
INDUCTIVE SIDE
OF RESONANCE
IL
LO
AVG*5
IMLS
Inductor
saturation
CAPACITIVE SIDE
OF RESONANCE
4.6V
VVCO
FREQUENCY SWEEP MODE
RUN MODE FAULT MODE
Fig. 8 Crest factor protection timing diagram
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www.ds-imp.com.cn
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