|
|
PDF P3P622S01J Data sheet ( Hoja de datos )
| Número de pieza | P3P622S01J | |
| Descripción | Peak EMI Reduction IC | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de P3P622S01J (archivo pdf) en la parte inferior de esta página. Total 6 Páginas | ||
|
No Preview Available !
P3P622S01J
Timing-Safet
Peak EMI Reduction IC
Functional Description
P3P622S01J is a versatile, 3.3 V Zero−delay buffer designed to
distribute low frequency Timing−Safe Clocks with Peak EMI
Reduction.
P3P622S01J accepts an input clock either from a fundamental
Crystal or from an external reference clock.
P3P622S01J accepts one reference input and drives out two
low−skew clocks.
P3P622S01J has an on−chip PLL that locks to an input reference
clock. The PLL feedback is on−chip and is obtained from the
CLKOUT pad, internal to the device.
Multiple P3P622S01J devices can accept the same input clock and
distribute it. In this case, the skew between the outputs of the two
devices is guaranteed to be less than 700 pS.
The output has less than 200 pS of cycle−to−cycle jitter. The input
and output propagation delay is guaranteed to be less than 250 pS, and
the output−to−output skew is guaranteed to be less than 250 pS.
Refer “Spread Spectrum Control and Input−Output Skew Table” for
deviations and Input−Output Skew.
General Features
• Low Frequency Clock Distribution with Timing−Safe Peak EMI
Reduction
• Input Frequency Range: 4 MHz − 20 MHz
• Zero Input − Output Propagation Delay
• Low−skew Outputs:
♦ Output−output Skew Less than 250 pS
♦ Device−device Skew Less than 700 pS
• Less than 200 pS Cycle−to−cycle Jitter
• Available in 8 Pin, 4.4 mm TSSOP Package
• Supply Voltage: 3.3 V ± 0.3 V
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
www.onsemi.com
TSSOP8 4.4x3
CASE 948AL
PIN CONFIGURATION
XIN / CLKIN 1
8 CLKOUT2
XOUT 2
SS% 3
P3P622S01J
7 VDD
6 CLKOUT1
GND 4
5 SSON
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
Spread Spectrum Frequency Generation
The clocks in digital systems are typically square waves
with a 50% duty cycle and as frequencies increase the edge
rates also get faster. Analysis shows that a square wave is
composed of fundamental frequency and harmonics. The
fundamental frequency and harmonics generate the energy
peaks that become the source of EMI. Regulatory agencies
test electronic equipment by measuring the amount of peak
energy radiated from the equipment. In fact, the peak level
allowed decreases as the frequency increases. The standard
methods of reducing EMI are to use shielding, filtering,
multi−layer PCBs etc. These methods are expensive. Spread
spectrum clocking reduces the peak energy by reducing the
Q factor of the clock. This is done by slowly modulating the
clock frequency.P3P622S01J uses the center modulation
spread spectrum technique in which the modulated output
frequency varies above and below the reference frequency
with a specified modulation rate. With center modulation,
the average frequency is the same as the unmodulated
frequency and there is no performance degradation.
Timing−Safe Technology
Timing−Safe technology is the ability to modulate a clock
source with Spread Spectrum technology and maintain
synchronization with any associated data path.
© Semiconductor Components Industries, LLC, 2014
October, 2014 − Rev. 2
1
Publication Order Number:
P3P622S01J/D
1 page  
P3P622S01J
INPUT
OUTPUT
VDD/2
VDD/2
t6
Figure 6. Input−Output Propagation Delay
CLKOUT, Device 1
CLKOUT, Device 2
VDD/2
VDD/2
t7
Figure 7. Device−Device Skew
Timing−Safet
Input
Output
TSKEW−ÉÉÉÉÉÉÉÉÉÉÉÉTSKEW+ÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉ
One clock cycle
TSKEW represents input−output skew
when spread spectrum is ON
For example, TSKEW = ± 0.125 for an
Input clock12MHz, translates in to
(1/12MHz) * 0.125=10.41nS
Figure 8. Input−Output Skew
Input
+3.3 V
OUTPUTS
VDD
0.1 mF
GND
Figure 9. Test Circuit
Input
CLKOUT
CLOAD
CLKOUT with SSOFF
Timing−Safet CLKOUT
Figure 10. A Typical Example of Timing−Safe Waveform
Table 7. ORDERING INFORMATION
Part Number
Marking
Package Type
Temperature
P3P622S01JG−08TR
ADS
8 pin, 4.4 mm TSSOP, TAPE & REEL, Green
0°C to +70°C
NOTE: A “microdot” placed at the end of last row of marking or just below the last row toward the center of package indicates Pb−free
http://onsemi.com
5
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet P3P622S01J.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| P3P622S01J | Peak EMI Reduction IC | ON Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |