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PDF LE24CBK23MC Data sheet ( Hoja de datos )

Número de pieza LE24CBK23MC
Descripción Dual port EEPROM Two Wire Serial Interface
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No Preview Available ! LE24CBK23MC Hoja de datos, Descripción, Manual

Ordering number: ENA2069
LE24CBK23MC
CMOS IC
Dual port EEPROM
Two Wire Serial Interface
(2K+2K EEPROM)
http://onsemi.com
Overview
The dual port EEPROM series consists of two independent banks, and each bank can be controlled separately using
dedicated control pins. The two banks can each be controlled separately, but share the internal power supply system.
In addition, this product uses a 2-wire serial interface, and is the optimal device for realizing substantial reductions in
system cost and mounting area, as well as low power consumption.
This product also incorporates a combine mode that allows the two-bank configuration (2K bits + 2K bits) to be used
as a pseudo-one-bank configuration (4K bits) by setting the COBM# pin to the low level. Together with the 16-byte
page write function, this enables a reduction in the number of factory write processes.
This product incorporates high performance CMOS EEPROM technology and realizes high-speed operation and
high-level reliability. The interface of this product is compatible with the I2C bus protocol, making it ideal as a
nonvolatile memory for small-scale parameter storage.
In addition, this product also supports DDC2TM, so it can also be used as an EDID data storage memory for display
equipment.
Functions
Capacity
: 2K bits (256 × 8 bits) + 2K bits (256 × 8 bits): 4k bits in total
Bank configuration
: 2-Bank (2k-bit + 2k-bit)
Single supply voltage
Interface
: 2.5V to 5.5V
: Two wire serial interface (I2C Bus*), VESA DDC2TM compliant**
Operating clock frequency : 400kHz (max)
Low power consumption : Standby: 5μA (max)
: One-bank read: 0.8 mA (max.)
Automatic page write mode : 16 bytes
Read mode
Erase/Write cycles
: Sequential read and random read
: 106 cycles
Data Retention
: 20 years
Default data
: FFh(All address)
High reliability
: Adopts proprietary symmetric memory array configuration
(USP6947325)
Noise filters connected to SCL1, SDA1, SCL2 and SDA2 pins
Incorporates a feature to prohibit write operations under low voltage conditions.
* : I2C Bus is a trademark of Philips Corporation.
** : DDC and EDID are trademarks of Video Electronics Standard Association (VESA).
* This product is licensed from Silicon Storage Technology, Inc. (USA).
Semiconductor Components Industries, LLC, 2013
July, 2013
62012 SY 20120111-S00002 No.A2069-1/21

1 page




LE24CBK23MC pdf
AC Electric Characteristics
Fast Mode
Parameter
Slave mode SCL clock frequency
SCL clock low time
SCL clock high time
SDA output delay time
SDA data output hold time
Start condition setup time
Start condition hold time
Data in setup time
Data in hold time
Stop condition setup time
SCL, SDA rise time
SCL, SDA fall time
Bus release time
Noise suppression time
Write cycle time
Standard Mode
Parameter
Slave mode SCL clock frequency
SCL clock low time
SCL clock high time
SDA output delay time
SDA data output hold time
Start condition setup time
Start condition hold time
Data in setup time
Data in hold time
Stop condition setup time
SCL, SDA rise time
SCL, SDA fall time
Bus release time
Noise suppression time
Write cycle time
LE24CBK23MC
Symbol
fSCLS
tLOW
tHIGH
tAA
tDH
tSU.STA
tHD.STA
tSU.DAT
tHD.DAT
tSU.STO
tR
tF
tBUF
tSP
tWC
Symbol
fSCLS
tLOW
tHIGH
tAA
tDH
tSU.STA
tHD.STA
tSU.DAT
tHD.DAT
tSU.STO
tR
tF
tBUF
tSP
tWC
VDD=2.5V to 5.5V
min typ
1200
600
100
100
600
600
100
0
600
1200
max
400
900
300
300
100
5
unit
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
VDD=2.5V to 5.5V
min typ
4700
4000
100
100
4700
4000
250
0
4000
4700
max
100
3500
1000
300
100
5
unit
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
No.A2069-5/21

5 Page





LE24CBK23MC arduino
LE24CBK23MC
7 EEPROM write operation
7-1. Byte writing
When the EEPROM receives the 7-bit device address and write command code “0” after the start condition, it
generates an acknowledge signal. After this, if it receives the 8-bit word address, generates an acknowledge signal,
receives the 8-bit write data, generates an acknowledge signal and then receives the stop condition, the internal write
operation of the EEPROM in the designated memory address will start. Rewriting is completed in the tWC period
after the stop condition. During an EEPROM internal write operation, no input is accepted and no acknowledge
signals are generated.
Word Address
SDA
S0
1 0 1 0 S2 S1 / W
A8
A7 A6 A5 A4 A3 A2 A1 A0
ACK
R/W
Bank mode : S2, S1, S0 is effective.
Combine mode : A8 is effective. S2 and S1 are Don’t care
Data
D7 D6 D5 D4 D3 D2 D1 D0
ACK
ACK
Access from master
7-2. Page writing
This product enables pages with up to 16 bytes to be written. The basic data transfer procedure is the same as for byte
writing: Following the start condition, the 7-bit device address and write command code “0,” word address (n), and
data (n) are input in this order while confirming acknowledge “0” every 9 bits. The page write mode is established if,
after data (n) is input, the write data (n+1) is input without inputting the stop condition. After this, the write data
equivalent to the largest page size can be received by a continuous process of repeating the receiving of the 8-bit
write data and generating the acknowledge signals.
At the point when the write data (n+1) has been input, the lower 4 bits (A0-A3) of the word addresses are
automatically incremented to form the (n+1) address. In this way, the write data can be successively input, and the
word address on the page is incremented each time the write data is input. If the write data exceeds 16 bytes or the
last address of the page is exceeded, the word address on the page is rolled over. Write data will be input into the
same address two or more times, but in such cases the write data that was input last will take effect. Finally, the
EEPROM internal write operation corresponding to the page size for which the write data is received starts from the
designated memory address when the stop condition is received.
SDA
Memory Address(n)
S0
1 0 1 0 S2 S1 / W
A8
A7 A6 A5 A4 A3 A2 A1 A0
ACK
R/W
Data(n)
D7 D6 D5 D4 D3 D2 D1 D0
ACK
Data(n+x)
Data(n+1)
D7 D6 D1 D0
ACK
ACK
D7 D6 D1 D0 D7 D6 D1 D0
ACK
Bank mode : S2, S1, S0 is effective.
Combine mode : A8 is effective. S2 and S1 are Don’t care
D7 D6 D1 D0 D7 D6 D1 D0
ACK
ACK
Access from master
No.A2069-11/21

11 Page







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