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PDF FEDL9058E Data sheet ( Hoja de datos )
| Número de pieza | FEDL9058E | |
| Descripción | 132-Channel LCD Driver | |
| Fabricantes | LAPIS | |
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LAPIS Semiconductor
FEDL9058E-01
Issue Date: April. 13, 2007
ML9058E
132-Channel LCD Driver with Built-in RAM for LCD Dot Matrix Displays
GENERAL DESCRIPTION
The ML9058E is an LSI for dot matrix graphic LCD devices carrying out bit map display. This LSI can drive a dot
matrix graphic LCD display panel under the control of an 8-bit microcomputer (hereinafter described MPU).
Since all the functions necessary for driving a bit map type LCD device are incorporated in a single chip, using the
ML9058E makes it possible to realize a bit map type dot matrix graphic LCD display system with only a few chips.
Since the bit map method in which one bit of display RAM data turns ON or OFF one dot in the display panel, it is
possible to carry out displays with a high degree of freedom such as Chinese character displays, etc. With one chip,
it is possible to construct a graphic display system with a maximum of 65 132 dots. The display can be expanded
further using two chips. However, the ML9058E is not used in a multiple chip configuration when a line reversal
drive is set.
The ML9058E is made using a CMOS process. Because it has a built-in RAM, low power consumption is one of
its features, and is therefore suitable for displays in battery-operated portable equipment.
The ML9058E has 65 common signal outputs and 132 segment signal outputs and one chip can drive a display of
up to 65 132 dots.
FEATURES
Direct display of the RAM data using the bit map method
Display RAM data “1” ... Dot is displayed
Display RAM data “0” ... Dot is not displayed (during forward display)
Display RAM capacity
65 132 = 8580 bits
LCD Drive circuits
65 common outputs, 132 segment outputs
MPU interface: Can select an 8-bit parallel or serial interface
Built-in voltage multiplier circuit for the LCD drive power supply
Built-in LCD drive voltage adjustment circuit
Built-in LCD drive bias generator circuit
Can select frame reversal drive or line reversal drive by command
Built-in oscillator circuit (Internal RC oscillator/external clock input)
A variety of commands
Read/write of display data, display ON/OFF, forward/reverse display, all dots ON/all dots OFF, set page
address, set display start address, etc.
Power supply voltage
Logic power supply: VDD-VSS = 3.7 V to 5.5 V
Voltage multiplier reference voltage: VIN-VSS = 3.7 V to 5.5 V
(2- to 4-time multiplier available)
LCD Drive voltage: VBI-VSS = 6.0 to 18 V
Package: Gold bump chip (Bump hardness: Low, DV)
: Gold bump chip (Bump hardness: High, CV)
This device is not resistant to radiation and light.
1/76
1 page  
LAPIS Semiconductor
FEDL9058E-01
ML9058E
ELECTRICAL CHARACTERISTICS
DC Characteristics
Parameter
“H” Input voltage
“L” Input voltage
“H” Input voltage
“L” Input voltage
Hysteresis width
“H” output voltage
“L” output voltage
“H” Input current
“L” Input current
Input capacitance
V1 output voltage
temperature gradient
Reference voltage
V1 output voltage
Voltage multiplier
output voltage
VOUT - V1 voltage
LCD driver ON
resistance
Oscillator
frequency
Internal
oscillation
External
input
Symbol
Condition
VIH
VIL
VIH
VIL
V
VOH
VOL
IIH
IIL
CI
V1TC
VREG
V1
VOUT
Vot1
VDD = 4.5 to 5.5 V
IOH = –0.5 mA
IOL = 0.5 mA
VI = VDD
VI = 0 V
Tj=25°C
F=10kHz
Tj = 25°C
V1 = 12 V
Tj = 25°C
*6
3-time
multiplication *7
4-time
multiplication *8
*9
RON IO = 50 µA
fOSC
fEXT
Tj = 25°C
[VSS = 0 V, VDD = 3.7 to 5.5 V, Tj =–40 to +85°C]
Min
Typ
Max
Unit
Applicable
pins
0.8 VDD
0
— VDD
— 0.2 VDD
V
*1
0.8 VDD —
VDD
0 — 0.2 VDD V
*2
0.85 1.0 1.55
0.8 VDD
—
——
— 0.2 VDD
V
*3
–1.0 — +1.0
A
–3.0 — +3.0
*4 *5
— 8 12 pF *1, *2
–0.03
2.925
10.58
13.0
–0.05
3.00
10.85
—
–0.08
3.075
11.12
—
%/°C
V
V
V
V1
VRS
V1
VOUT
15.9 —
—
V
VOUT
0.6 — — V VOUT, V1
SEG1 to 131,
— — 10 k COMS0,
COMS1,
COM0 to 63
18 22 26 kHz
*10
14 — 31 kHz
18 22 26 kHz CL*10
*1: DB0 to DB5, DB7 (SI), FR, DOF Pins
*2: A0, CS1, CS2, CLS, M/S, C86, P/S, IRS,RD (E), WR (R/W), RES, CL, DB6 (SCL) Pins
*3: DB0 to DB7, FR, FRS, DOF, CL Pins
*4: A0, RD (E), WR (R/W), CS1, CS2, CLS, M/S, C86, P/S, RES, IRS Pins
*5: Applicable to the pins DB0 to DB5, DB6 (SCL), DB7 (SI), CL, FR, DOF in the high impedance
state.
*6: Tj = 25°C, = 31, (1+Rb/Ra) = 4, VOUT = 13.5 V (External input), LCD drive output = no-load
*7: VIN = 4.8 V, voltage multiplier capacitor C1 = 2.6 to 4.0 F, voltage multiplier output load current
I = 500 A. Only a voltage multiplier circuit operates, not activating the voltage adjustment circuit
and V/F circuit, by command “2C”.
5/76
5 Page 
LAPIS Semiconductor
FEDL9058E-01
ML9058E
Parameter
Address hold time
Address setup time
System cycle time
Data setup time
Data hold time
Access time
Output disable time
Enable H pulse width
Enable L pulse width
Read
Write
Read
Write
Symbol
tAH6
tAW6
tCYC6
tDS6
tDH6
tACC6
tOH6
tEWHR
tEWHW
tEWLR
tEWLW
[VDD = 4.5 to 5.5 V, Tj = –40 to +85°C]
Condition
Rated value
Unit
Min Max
5—
5—
166 —
30 —
10 —
CL = 100 pF
— 70 ns
10 50
70 —
30 —
60 —
60 —
Parameter
Address hold time
Address setup time
System cycle time
Data setup time
Data hold time
Access time
Output disable time
Enable H pulse width
Enable L pulse width
Read
Write
Read
Write
Symbol
tAH6
tAW6
tCYC6
tDS6
tDH6
tACC6
tOH6
tEWHR
tEWHW
tEWLR
tEWLW
[VDD = 3.7 to 4.5 V, Tj = –40 to +85°C]
Condition
Rated value
Unit
Min Max
5—
5—
300 —
40 —
15 —
CL = 100 pF
— 140 ns
10 100
120 —
60 —
60 —
60 —
Note 1:
Note 2:
Note 3:
The input signal rise and fall times are specified as 15ns or less.
When using the system cycle time for fast speed, the specified values are (tr + tf) (tCYC6 –
tEWLW – tEWHW) or (tr + tf) (tCYC6 – tEWLR – tEWHR).
All timings are specified taking the levels of 20% and 80% of VDD as the reference.
The values of tEWLW and tEWLR are specified during the overlapping period of CS1 at “L” (CS2 =
“H”) and the “H” level of E.
11/76
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet FEDL9058E.PDF ] | |
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