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PDF EMG2DXV5 Data sheet ( Hoja de datos )

Número de pieza EMG2DXV5
Descripción Dual Bias Resistor Transistors
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EMG2DXV5, EMG5DXV5
Dual Bias Resistor
Transistors
NPN Silicon Surface Mount Transistors
with Monolithic Bias Resistor Network
This new series of digital transistors is designed to replace a single
device and its external resistor bias network. The BRT (Bias Resistor
Transistor) contains a single transistor with a monolithic bias network
consisting of two resistors; a series base resistor and a baseemitter
resistor. The BRT eliminates these individual components by
integrating them into a single device. The use of a BRT can reduce
both system cost and board space. The device is housed in the
SOT553 package which is designed for low power surface mount
applications.
Features
Simplifies Circuit Design
Reduces Board Space
Reduces Component Count
Moisture Sensitivity Level: 1
Available in 8 mm, 7 inch Tape and Reel
LeadFree Solder Plating
These Devices are PbFree, Halogen Free/BFR Free and are RoHS
Compliant
MAXIMUM RATINGS (TA = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Collector-Base Voltage
VCBO
50
Vdc
Collector-Emitter Voltage
VCEO
50
Vdc
Collector Current
IC 100 mAdc
THERMAL CHARACTERISTICS
Characteristic
Symbol
Max
Unit
Total Device Dissipation
TA = 25°C
Derate above 25°C
Thermal Resistance
Junction-to-Ambient
PD
RqJA
230 (Note 1)
338 (Note 2)
1.8 (Note 1)
2.7 (Note 2)
540 (Note 1)
370 (Note 2)
mW
°C/W
°C/W
Thermal Resistance
Junction-to-Lead
RqJL
264 (Note 1)
287 (Note 2)
°C/W
Junction and Storage
Temperature Range
TJ, Tstg 55 to +150
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. FR4 @ Minimum Pad
2. FR4 @ 1.0 x 1.0 inch Pad
http://onsemi.com
NPN SILICON
BIAS RESISTOR
TRANSISTORS
(5) (4)
Q1 Q2
R2 R2
R1 R1
(1) (2) (3)
5
1
SOT553
CASE 463B
MARKING
DIAGRAM
5
XXM G
G
1
XX = UF (EMG5)
UP (EMG2)
M = Date Code
G = PbFree Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
© Semiconductor Components Industries, LLC, 2013
March, 2013 Rev. 1
1
Publication Order Number:
EMG5DXV5/D

1 page




EMG2DXV5 pdf
EMG2DXV5, EMG5DXV5
TYPICAL APPLICATIONS FOR NPN BRTs
+12 V
FROM mP OR
OTHER LOGIC
ISOLATED
LOAD
Figure 12. Level Shifter: Connects 12 or 24 Volt Circuits to Logic
+12 V
VCC
OUT
IN
LOAD
Figure 13. Open Collector Inverter:
Inverts the Input Signal
Figure 14. Inexpensive, Unregulated Current Source
http://onsemi.com
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