PDF GS2994 Datasheet ( Hoja de datos )

Número de pieza GS2994
Descripción Adaptive Cable Equalizer
Fabricantes Semtech 
Logotipo Semtech Logotipo

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GS2994 Hoja de datos, Descripción, Manual
GS2994 Adaptive Cable Equalizer
Key Features
• SMPTE 424M, SMPTE 292M and SMPTE 259M
• Automatic cable equalization
• Multi-standard operation from 143Mb/s to 2.97Gb/s
• Performance optimized for 270Mb/s, 1.485Gb/s and
2.97Gb/s. Typical equalized length of Belden 1694A
Š 140m at 2.97Gb/s
Š 220m at 1.485Gb/s
Š 400m at 270Mb/s
• Supports DVB-ASI at 270Mb/s
• Manual bypass (useful for low data rates with slow
rise/fall times)
• Programmable carrier detect with squelch threshold
• Automatic power-down on loss of signal
Š Standby power <30mW (typical)
• Differential outputs support DC-coupling to 1.2V, 2.5V
and 3.3V CML logic
• 0/6 dB gain boost selection pin
• Selectable de-emphasis: 2dB, 4dB and 6dB
• Standard EIA/JEDEC logic control and status signal
• Single 3.3V power supply operation
• 167mW power consumption (typical)
• Wide operating temperature range of -40ºC to +85ºC
• Small footprint QFN package (4mm x 4mm)
Š Footprint compatible with the GS2974 and the
• Pb-free and RoHS compliant
• SMPTE 424M, SMPTE 292M and SMPTE 259M coaxial
cable serial digital interfaces
The GS2994 is a high-speed BiCMOS integrated circuit
designed to equalize and restore signals received over 75Ω
coaxial cable.
The device is designed to support SMPTE 424M,
SMPTE292M and SMPTE 259M, and is optimized for
performance at 270Mb/s, 1.485Gb/s and 2.97Gb/s.
The GS2994 features DC restoration to compensate for the
DC content of SMPTE pathological test patterns.
The Carrier Detect output pin (CD) indicates whether a
valid input signal has been detected. It can be connected
directly to the SLEEP pin to enable automatic power-down
upon loss of carrier. In the manual sleep mode, a voltage
programmable threshold, which can be changed via the
SQ_ADJ pin, forces CD high when the input signal
amplitude falls below the threshold. This allows the GS2994
to distinguish between low-amplitude SDI signals and
noise at the input of the device.
The equalizing and DC restore stages are disengaged when
the BYPASS pin is HIGH. No equalization occurs in Bypass
The GS2994 includes a gain selection pin (GAIN_SEL)
which, when tied HIGH, compensates for 6dB flat
The differential outputs can be DC-coupled to Gennum
3.3V cable drivers and reclockers and to industry-standard
1.2V, 2.5V and 3.3V CML logic using the VCC_O pin. In
general, DC-coupling to any termination voltage between
1.2V and 3.3V is supported.
The GS2994 also includes programmable de-emphasis with
three operating levels in order to support long PCB traces.
The GS2994 is footprint and drop-in compatible with
existing GS2974 and GS2984 designs.
The device is available in a 16-pin, 4mm x 4mm QFN
Power consumption of the GS2994 is typically 167mW
when DC-coupled at 1.2V.
The GS2994 is Pb-free, and the encapsulation compound
does not contain halogenated flame retardant.
This component and all homogeneous subcomponents are
RoHS compliant.
GS2994 GS2994 Adaptive Cable Equalizer
Data Sheet
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August 2012
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GS2994 pdf
Table 1-1: GS2994 Pin Descriptions (Continued)
Pin Number
10, 11
14 SLEEP Not Input
15 CD Not Output
Center Pad
Squelch Threshold Adjust.
Adjusts the input signal amplitude threshold of the carrier detect
function. The output can be muted when the input signal
amplitude is too low by connecting the CD and OP_CTL pins
together through some external components. In this case, when CD
is LOW (0V), OP_CTL is forced LOW (0V), and when CD is HIGH
(2.5V), OP_CTL is forced HIGH (3.3V). The input level at which the
part is muted can be set through the SQ_ADJ pin through suitable
voltage variances as described in Section 4.4. NOTE: when the
SQ_ADJ functionality is used and/or in auto_mute, the auto sleep
feature is not allowed, and the SLEEP pin should be left open.
Includes an internal pull-down resistor.
Controls the Output Swing, De-emphasis, and Mute features of the
SDO and SDO outputs.
When connected to GND, the output swing is 800mV with no
de-emphasis. When connected to the 3.3V analog power supply, the
output is MUTED.
Includes an internal pull down resistor.
See Section 4.7 for all other control options.
Equalized serial digital differential output.
Most negative power supply for the output buffer.
Connect to GND.
Most positive power supply connection for the output buffer of the
Connect to +1.2V ~ +3.3V DC.
When set HIGH, the GS2994 is powered-down except for the Carrier
Detect functionality.
Includes an internal pull-down resistor.
Carrier Detect status signal output.
Signal levels are LVCMOS/LVTTL compatible.
Indicates the presence of an input signal. When the CD pin is LOW, a
good input signal has been detected. When this pin is HIGH, the
input signal is invalid.
See Section 4.5.
Most positive power supply for the input buffer, core and control
circuits of the device.
Connect to +3.3V DC.
Internally bonded to VEE_A.
GS2994 GS2994 Adaptive Cable Equalizer
Data Sheet
53967 - 4
August 2012
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GS2994 arduino
4. Detailed Description
The GS2994 is a high-speed BiCMOS IC designed to equalize serial digital signals.
The GS2994 can equalize 3Gb/s, HD and SD serial digital signals, and will typically
equalize 140m of Belden 1694A cable at 2.97Gb/s, 220m at 1.485Gb/s and 400m at
270Mb/s. The GS2994 can be powered from a single +3.3V power supply, and is
footprint compatible with the GS2974 and GS2984 equalizers. When using 1.2V CML,
the GS2994 typically consumes approximately 167mW of power.
4.1 Serial Data Inputs
The Serial Data signal can be connected to the input pins (SDI/SDI) in either a differential
or single-ended configuration. AC-coupling of the inputs is recommended, as the SDI
and SDI inputs are internally biased at approximately 1.8V.
4.2 Cable Equalization
The input signal passes through a variable gain equalizing stage, whose frequency
response closely matches the inverse of the cable loss characteristic. In addition, the
variation of the frequency response with control voltage imitates the variation of the
inverse cable loss characteristic with cable length.
The edge energy of the equalized signal is monitored by a detector circuit which
produces an error signal corresponding to the difference between the desired edge
energy and the actual edge energy. This error signal is integrated by both an internal and
an external AGC filter capacitor providing a steady control voltage for the gain stage. As
the frequency response of the gain stage is automatically varied by the application of
negative feedback, the edge energy of the equalized signal is kept at a constant level
which is representative of the original edge energy at the transmitter. The equalized
signal is also DC-restored, effectively restoring the logic threshold of the equalized
signal to its correct level independent of shifts due to AC-coupling.
GS2994 GS2994 Adaptive Cable Equalizer
Data Sheet
53967 - 4
August 2012
11 of 20

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