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PDF GS2971A Data sheet ( Hoja de datos )

Número de pieza GS2971A
Descripción HD SD SDI Receiver
Fabricantes Semtech 
Logotipo Semtech Logotipo



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GS2971A
3Gb/s, HD, SD SDI Receiver, with Integrated Adaptive Cable Equalizer complete
with SMPTE Audio and Video Processing
Key Features
• Operation at 2.97Gb/s, 2.97/1.001Gb/s, 1.485Gb/s,
1.485/1.001Gb/s and 270Mb/s
• Supports SMPTE 425M (Level A and Level B), SMPTE
424M, SMPTE 292M, SMPTE 259M-C and DVB-ASI
• Integrated adaptive cable equalizer
• Typical equalized length of Belden 1694A cable:
Š 150m at 2.97Gb/s
Š 250m at 1.485Gb/s
Š 480m at 270Mb/s
• Integrated Reclocker with low phase noise, integrated
VCO
• Serial digital reclocked, or non-reclocked output
• Integrated audio de-embedder for 8 channels of 48kHz
audio
• Integrated audio clock generator
• Ancillary data extraction
• Optional conversion from SMPTE 425M Level B to
Level A for 1080p 50/60 4:2:2 10-bit
• Parallel data bus selectable as either 20-bit or 10-bit
• Comprehensive error detection and correction
features
• Output H, V, F or CEA 861 Timing Signals
• 1.2V digital core power supply, 1.2V and 3.3V analog
power supplies, and selectable 1.8V or 3.3V I/O power
supply
• GSPI Host Interface
• -20ºC to +85ºC operating temperature range
• Low power operation (typically 545mW)
• Small 11mm x 11mm 100-ball BGA package
• Pb-free and RoHS compliant
Applications
Application: Single Link (3G-SDI)
to Dual Link (HD-SDI) Converter
3G-SDI
GS2971A
10-bit
HV F/PCLK
GS2962/72
HV F/PCLK
10-bit
GS2962/72
HD-SDI
Link A
HD-SDI
Link B
3G-SDI
Application: 1080p50/60 Monitor
AES - OUT
GS2971A
AUDIO 1/2
AUDIO 3/4
AUDIO 5/6
AUDIO 7/8
Audio Clocks
Audio
Selector
10-bit
HV F/PCLK
Video
Processor
C TR L/TIMECODE
DAC
Speakers
DAC
Display
Application: Multi-format Downconverter
10-bit bit SD Bypass
Memory
SD/HD/3G-SDI
GS2971A
10-bit
HV F/PCLK
Video
Downconverter &
Aspect Ratio
Conversion
Analog
Sync
Sync
Seperator
AE S 1/2
AE S 3/4
AE S 5/6
AE S 7/8
Audio
Processing
& Delay
GS4901
Audio Clocks
HV F/PCLK
AE S 1/2
AE S 3/4
AE S 5/6
AE S 7/8
10-bit
HD/SD
Serializer
(GS1582,
GS1672)
SD-SDI
GS2971A 3Gb/s, HD, SD SDI Receiver
Data Sheet
54311 - 2
September 2012
www.semtech.com
1 of 152

1 page




GS2971A pdf
4.13.1 2K Support......................................................................................................................... 63
4.14 Data Format Detection & Indication ..................................................................................... 63
4.15 EDH Detection .............................................................................................................................. 64
4.15.1 EDH Packet Detection ................................................................................................... 64
4.15.2 EDH Flag Detection ........................................................................................................ 65
4.16 Video Signal Error Detection & Indication ......................................................................... 65
4.16.1 TRS Error Detection........................................................................................................ 67
4.16.2 Line Based CRC Error Detection ................................................................................ 67
4.16.3 EDH CRC Error Detection............................................................................................. 68
4.16.4 HD & 3G Line Number Error Detection ................................................................... 68
4.17 Ancillary Data Detection & Indication ................................................................................. 68
4.17.1 Programmable Ancillary Data Detection................................................................ 70
4.17.2 SMPTE 352M Payload Identifier ................................................................................ 71
4.17.3 Ancillary Data Checksum Error ................................................................................. 72
4.17.4 Video Standard Error..................................................................................................... 73
4.18 Signal Processing ......................................................................................................................... 73
4.18.1 TRS Correction & Insertion........................................................................................... 74
4.18.2 Line Based CRC Correction & Insertion ................................................................... 75
4.18.3 Line Number Error Correction & Insertion ............................................................. 75
4.18.4 ANC Data Checksum Error Correction & Insertion ............................................. 75
4.18.5 EDH CRC Correction & Insertion ............................................................................... 75
4.18.6 Illegal Word Re-mapping ............................................................................................. 76
4.18.7 TRS and Ancillary Data Preamble Remapping...................................................... 76
4.18.8 Ancillary Data Extraction............................................................................................. 76
4.18.9 Level B to Level A Conversion .................................................................................... 80
4.19 Audio De-embedder ................................................................................................................... 81
4.19.1 Serial Audio Data I/O Signals...................................................................................... 81
4.19.2 Serial Audio Data Format Support ............................................................................ 83
4.19.3 Audio Processing............................................................................................................. 87
4.19.4 Error Reporting ................................................................................................................ 94
4.20 GSPI - HOST Interface ................................................................................................................ 94
4.20.1 Command Word Description ...................................................................................... 95
4.20.2 Data Read or Write Access........................................................................................... 96
4.20.3 GSPI Timing....................................................................................................................... 97
4.21 Host Interface Register Maps .................................................................................................. 99
4.21.1 Video Core Registers...................................................................................................... 99
4.21.2 SD Audio Core Registers............................................................................................. 113
4.21.3 HD and 3G Audio Core Registers............................................................................. 128
4.22 JTAG Test Operation ................................................................................................................ 143
4.23 Device Power-up ....................................................................................................................... 145
4.24 Device Reset ................................................................................................................................ 145
4.25 Standby Mode ............................................................................................................................ 145
5. Application Reference Design ............................................................................................................. 146
5.1 High Gain Adaptive Cable Equalizers .................................................................................. 146
5.2 PCB Layout ..................................................................................................................................... 146
5.3 Typical Application Circuit ......................................................................................................147
6. References & Relevant Standards ....................................................................................................... 148
GS2971A 3Gb/s, HD, SD SDI Receiver
Data Sheet
54311 - 2
September 2012
5 of 152

5 Page





GS2971A arduino
Table 1-1:Pin Descriptions (Continued)
Pin
Number
Name
Timing
Type
Description
A9, A10, B8,
B9, B10,C8,
C9, C10, E9,
E10
DOUT18, 17, 19,
16, 15, 12, 14, 13,
10, 11
B1
B2, C3, C4
B3, F2
B4
B7, D9, G9,
J7
C1, D1
C2, D2, D3,
E3, F3, G2
A_VDD
PLL_VDD
RSV
VCO_GND
IO_GND
SDI, SDI
A_GND
Output
Input Power
Input Power
Input Power
Input Power
PARALLEL DATA BUS
Please refer to the Output Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
20-bit mode
20bit/10bit = HIGH
SMPTE mode (SMPTE_BYPASS = HIGH
and DVB_ASI = LOW):
Luma data output for SD and HD data
rates; Data Stream 1 for 3G data rate
DVB-ASI mode (SMPTE_BYPASS = LOW
and DVB_ASI = HIGH):
Not defined
Data-Through mode (SMPTE_BYPASS =
LOW and DVB_ASI = LOW):
Data output
10-bit mode
20bit/10bit = LOW
SMPTE mode (SMPTE_BYPASS = HIGH
and DVB_ASI = LOW):
Multiplexed Luma/Chroma data output
for SD and HD data rates; Multiplexed
Data Stream 1&2 for 3G data rate
DVB-ASI mode (SMPTE_BYPASS = LOW
and DVB_ASI = HIGH):
8b/10b decoded DVB-ASI data
Data-Through mode (SMPTE_BYPASS =
LOW and DVB_ASI = LOW):
Data output
POWER pin for analog circuitry. Connect to 3.3V DC analog.
POWER pins for the Reclocker PLL. Connect to 1.2V DC analog.
These pins must be left unconnected.
GND pin for the VCO. Connect to analog GND.
GND connection for digital I/O. Connect to digital GND.
Analog Input Serial Digital Differential Input.
Input Power GND pins for sensitive analog circuitry. Connect to analog GND.
GS2971A 3Gb/s, HD, SD SDI Receiver
Data Sheet
54311 - 2
September 2012
11 of 152

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