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PDF GS1671A Data sheet ( Hoja de datos )

Número de pieza GS1671A
Descripción HD/SD SDI Receiver
Fabricantes Semtech 
Logotipo Semtech Logotipo



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GS1671A
HD/SD SDI Receiver, with Integrated Adaptive Cable Equalizer complete with
SMPTE Audio and Video Processing
Key Features
• Operation at 1.485Gb/s, 1.485/1.001Gb/s and 270Mb/s
• Supports SMPTE 292M, SMPTE 259M-C and DVB-ASI
• Integrated adaptive cable equalizer
• Typical equalized length of Belden 1694A cable:
Š 230m at 1.485Gb/s
Š 440m at 270Mb/s
• Integrated Reclocker with low phase noise, integrated
VCO
• Serial digital reclocked, or non-reclocked output
• Integrated audio de-embedder for 8 channels of 48kHz
audio
• Integrated audio clock generator
• Ancillary data extraction
• Parallel data bus selectable as either 20-bit or 10-bit
• Comprehensive error detection and correction
features
• Output H, V, F or CEA 861 Timing Signals
• 1.2V digital core power supply, 1.2V and 3.3V analog
power supplies, and selectable 1.8V or 3.3V I/O power
supply
• GSPI Host Interface
• Wide temperature range of -40ºC to +85ºC
• Low power operation (typically 480mW)
• Small 11mm x 11mm 100-ball BGA package
• Pb-free and RoHS compliant
Applications
Application: 1080p30 or 720p60 Monitor
HD-SDI
AES - OUT
GS1671A
AUDIO 1/2
AUDIO 3/4
AUDIO 5/6
AUDIO 7/8
Audio Clocks
Audio
Selector
10-bit
HV F/PCLK
Video
Processor
C TR L/TIMECODE
DAC
Speakers
DAC
Display
Application: Multi-format Downconverter
10-bit SD Bypass
Memory
SD/HD-SDI
GS1671A
10-bit
HV F/PCLK
Video
Downconverter &
Aspect Ratio
Conversion
Analog
Sync
Sync
Seperator
AE S 1/2
AE S 3/4
AE S 5/6
AE S 7/8
Audio
Processing
& Delay
GS4901
Audio Clocks
HV F/PCLK
AE S 1/2
AE S 3/4
AE S 5/6
AE S 7/8
10-bit
HD/SD
Serializer
(GS1672)
HD/SD-SDI
Application: Multi-input Video Monitoring System
HD-SDI
Input 1
HD-SDI
Input 2
GS1671A
10-bit
HV F/PCLK
GS1671A
10-bit
HV F/PCLK
Video
Memory
Video
Formatter
H V/DE/PCLK
DVI/
VGA DAC
Video
Output
HD-SDI
Input n
GS1671A
10-bit
HV F/PCLK
Analog
Sync
Sync
Seperator
AES BUS
GS4911
Audio
Select
HV F/PCLK
Audio Clocks
On Screen
Display
Generator
Audio
Processor
AE S OUT 1/2
AE S OUT 3/4
AE S OUT 5/6
AE S OUT 7/8
GS1671A HD/SD SDI Receiver
Data Sheet
54389 - 1
September 2012
www.semtech.com
1 of 136

1 page




GS1671A pdf
4.15 Video Signal Error Detection & Indication ......................................................................... 56
4.15.1 TRS Error Detection........................................................................................................ 57
4.15.2 Line Based CRC Error Detection ................................................................................ 57
4.15.3 EDH CRC Error Detection............................................................................................. 58
4.15.4 HD Line Number Error Detection .............................................................................. 58
4.16 Ancillary Data Detection & Indication ................................................................................. 59
4.16.1 Programmable Ancillary Data Detection................................................................ 60
4.16.2 SMPTE 352M Payload Identifier ................................................................................ 61
4.16.3 Ancillary Data Checksum Error ................................................................................. 61
4.16.4 Video Standard Error..................................................................................................... 62
4.17 Signal Processing ......................................................................................................................... 63
4.17.1 TRS Correction & Insertion........................................................................................... 64
4.17.2 Line Based CRC Correction & Insertion ................................................................... 64
4.17.3 Line Number Error Correction & Insertion ............................................................. 64
4.17.4 ANC Data Checksum Error Correction & Insertion ............................................. 64
4.17.5 EDH CRC Correction & Insertion ............................................................................... 64
4.17.6 Illegal Word Re-mapping ............................................................................................. 65
4.17.7 TRS and Ancillary Data Preamble Remapping...................................................... 65
4.17.8 Ancillary Data Extraction............................................................................................. 65
4.18 Audio De-embedder ................................................................................................................... 69
4.18.1 Serial Audio Data I/O Signals...................................................................................... 69
4.18.2 Serial Audio Data Format Support ............................................................................ 71
4.18.3 Audio Processing............................................................................................................. 75
4.18.4 Error Reporting ................................................................................................................ 82
4.19 GSPI - HOST Interface ................................................................................................................ 83
4.19.1 Command Word Description ...................................................................................... 83
4.19.2 Data Read or Write Access........................................................................................... 84
4.19.3 GSPI Timing....................................................................................................................... 85
4.20 Host Interface Register Maps .................................................................................................. 87
4.20.1 Video Core Registers...................................................................................................... 87
4.20.2 SD Audio Core Registers............................................................................................... 96
4.20.3 HD Audio Core Registers............................................................................................ 111
4.21 JTAG Test Operation ................................................................................................................ 127
4.22 Device Power-up ....................................................................................................................... 129
4.23 Device Reset ................................................................................................................................ 129
4.24 Standby Mode ............................................................................................................................ 129
5. Application Reference Design ............................................................................................................. 130
5.1 High Gain Adaptive Cable Equalizers .................................................................................. 130
5.2 PCB Layout ..................................................................................................................................... 130
5.3 Typical Application Circuit ......................................................................................................131
6. References & Relevant Standards ....................................................................................................... 132
7. Package & Ordering Information ........................................................................................................ 133
7.1 Package Dimensions ................................................................................................................... 133
7.2 Packaging Data ............................................................................................................................. 134
7.3 Marking Diagram ......................................................................................................................... 134
7.4 Solder Reflow Profiles ................................................................................................................ 135
7.5 Ordering Information ................................................................................................................. 135
Revision History ............................................................................................................................................ 135
GS1671A HD/SD SDI Receiver
Data Sheet
54389 - 1
September 2012
5 of 136

5 Page





GS1671A arduino
Table 1-1: Pin Descriptions (Continued)
Pin
Number
D5, E5, F5,
G4, G5
D6, E6, F6,
G6
D7
D8
E1
E2
E7
E8
F1, G1
Name
Timing
Type
Description
CORE_GND
CORE_VDD
SW_EN
JTAG/HOST
EQ_VDD
EQ_GND
SDOUT_TDO
SDIN_TDI
AGCP, AGCN
Input Power GND connection for device core. Connect to digital GND.
Input Power POWER connection for device core. Connect to 1.2V DC digital.
Input
Input
Input Power
Input Power
Output
Input
CONTROL SIGNAL INPUT
Please refer to the Input Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
Used to enable switch-line locking, as described in Section 4.9.1.
CONTROL SIGNAL INPUT
Please refer to the Input Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
Used to select JTAG test mode or host interface mode.
When JTAG/HOST is HIGH, the host interface port is configured for
JTAG test.
When JTAG/HOST is LOW, normal operation of the host interface
port resumes.
POWER pin for SDI buffer. Connect to 3.3V DC analog.
GND pin for SDI buffer. Connect to analog GND.
COMMUNICATION SIGNAL OUTPUT
Please refer to the Output Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
GSPI serial data output/test data out.
In JTAG mode (JTAG/HOST = HIGH), this pin is used to shift test
results from the device.
In host interface mode, this pin is used to read status and
configuration data from the device.
Note: GSPI is slightly different than the SPI. For more details on GSPI,
please refer to 4.19 GSPI - HOST Interface.
COMMUNICATION SIGNAL INPUT
Please refer to the Input Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
GSPI serial data in/test data in.
In JTAG mode (JTAG/HOST = HIGH), this pin is used to shift test data
into the device.
In host interface mode, this pin is used to write address and
configuration data words into the device.
Automatic Gain Control for the equalizer. Attach the AGC capacitor
between these pins.
GS1671A HD/SD SDI Receiver
Data Sheet
54389 - 1
September 2012
11 of 136

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