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PDF FCP25N60N Data sheet ( Hoja de datos )

Número de pieza FCP25N60N
Descripción N-Channel SupreMOS MOSFET
Fabricantes Fairchild Semiconductor 
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FCP25N60N
N-Channel SupreMOS® MOSFET
600 V, 25 A, 125 mΩ
November 2013
Features
• RDS(on) = 107 mΩ (Typ.) @ VGS = 10 V, ID = 12.5 A
• Ultra Low Gate Charge (Typ. Qg = 57 nC)
• Low Effective Output Capacitance (Typ. Coss(eff.) = 262 pF)
• 100% Avalanche Tested
• RoHS Compliant
Application
• Solar Inverter
• AC-DC Power Supply
Description
The SupreMOS® MOSFET is Fairchild Semiconductor’s next
generation of high voltage super-junction (SJ) technology
employing a deep trench filling process that differentiates it from
the conventional SJ MOSFETs. This advanced technology and
precise process control provides lowest Rsp on-resistance,
superior switching performance and ruggedness. SupreMOS
MOSFET is suitable for high frequency switching power con-
verter applications such as PFC, server/telecom power, FPD TV
power, ATX power, and industrial power applications.
D
GDS TO-220
G
S
Absolute Maximum Ratings TC = 25oC unless otherwise noted.
Symbol
VDSS
VGSS
ID
IDM
EAS
IAR
EAR
dv/dt
PD
TJ, TSTG
TL
Parameter
Drain to Source Voltage
Gate to Source Voltage
Drain Current
Drain Current
- Continuous (TC = 25oC)
- Continuous (TC = 100oC)
- Pulsed
(Note 1)
Single Pulsed Avalanche Energy
(Note 2)
Avalanche Current
(Note 1)
Repetitive Avalanche Energy
(Note 1)
Peak Diode Recovery dv/dt
(Note 3)
MOSFET dv/dt
Power Dissipation
(TC = 25oC)
- Derate Above 25oC
Operating and Storage Temperature Range
Maximum Lead Temperature for Soldering, 1/8” from Case for 5 Seconds
FCP25N60N_F102
600
±30
25
16
75
861
8.3
2.2
20
100
216
1.72
-55 to +150
300
Thermal Characteristics
Symbol
RθJC
RθJA
Parameter
Thermal Resistance, Junction to Case, Max.
Thermal Resistance, Junction to Ambient, Max.
FCP25N60N_F102
0.58
62.5
Unit
V
V
A
A
mJ
A
mJ
V/ns
W
W/oC
oC
oC
Unit
oC/W
©2010 Fairchild Semiconductor Corporation
FCP25N60N Rev. C1
1
www.fairchildsemi.com

1 page




FCP25N60N pdf
IG = const.
Figure 12. Gate Charge Test Circuit & Waveform
V10GVS
VDS
VGS
RG
RL
VDD
VDS
90%
DUT
VGS 10%
td(on)
tr
t on
Figure 13. Resistive Switching Test Circuit & Waveforms
td(off)
tf
t off
VGS
Figure 14. Unclamped Inductive Switching Test Circuit & Waveforms
©2010 Fairchild Semiconductor Corporation
FCP25N60N Rev. C1
5
www.fairchildsemi.com

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