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PDF CH7034B Data sheet ( Hoja de datos )

Número de pieza CH7034B
Descripción HDTV/VGA/LVDS Encoder
Fabricantes Chrontel 
Logotipo Chrontel Logotipo



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Chrontel
CH7034B
Brief Datasheet
CH7034B HDTV/VGA/LVDS Encoder
FEATURES
GENERAL DESCRIPTIONS
Supports multiple output display formats – including Chrontel CH7034B is specifically designed for a portable
Component YPrPb(HDTV), LVDS and analog RGB system that requires connections to LCD display, High
(VGA)
Definition Television (HDTV) or RGB (VGA) monitor.
Three 10-bit high speed DACs
With its advanced video encoder, flexible scaling engine
HDTV output support up to 1080p
and easy-to-configure video interface, the CH7034B
Analog RGB (VGA) support up to 1920x1080 satisfies manufactures’ product display requirements and
resolution
reduces their costs of development and time-to-market.
Single channel LVDS 18-bit transmitter supports
input resolution up to 1366x768
The CH7034B provides analog RGB and YPrPb outputs
Support scaled and bypassed video streams output that allow a system to display high definition media
from VGA/HDTV and LVDS interfaces content to HDTV/RGB monitors. The device is
simultaneously
compliant with EIA770-3 and SMPTE 274M/293M
Supports panel protection, power sequencing and /296M standards and supports HDTV resolution up to
backlight on/off. PWM is available for controlling 1080p. The 3 high-performance, 10-bit DACs can be
LCD brightness
used for either HDTV display or VGA output. The
TV/Monitor connection detect capability. DACs can CH7034B has the ability to generate composite syncs if
be switched off through programming internal required by the RGB monitor.
registers
On-chip SDRAM frame buffer to support frame rate To support portable computer with LCD display, the
conversion.
CH7034B has incorporated an one-channel, 18-bit output
Programmable adaptive de-flickering filter
LVDS transmitter. On-chip dithering function is
Supports 8/12/16/18/24-bit parallel interface inputs available to convert 24-bit color to 18-bit color LCD
for either RGB format or YCbCr format (ITU-R 656 panels. Two popular LVDS standards, the OpenLDI and
or ITU-R 601). 80/86 MPU interface and DE only the VESA SPWG are supported by the CH7034B LVDS
mode are also supported.
driver. The preferred standard and its display timing can
Wide range of input resolutions support for up to be configured through devices’ registers when system is
1366x768 (i.e. 640x480 720x480, 720x576, 800x600, powered on.
1024x600, 1024x768, 1280x800, and etc.)
Image display rotation support at 90/180/270 degree The CH7034B is equipped with panel protection
or flipped in horizontal/vertical position
mechanism to switch off the LCD instantly if input data
Pixel-level color enhancement for brightness, is missing or unstable. The panel on/off sequences and
contrast, hue and saturation adjustment for HDTV backlight control can be configured through
Horizontal/vertical position adjusted through serial programming internal registers. In addition, a built-in
port programming
PWM function can be used to achieve digital dimming
Pixel clock input frequency support for up to 165 for LCD panel.
MHz
Flexible crystal or oscillator clock input frequency The CH7034B converts a wide range of input formats to
(2.3MHz – 64MHz)
HDTV/VGA outputs and LVDS display. RGB data
IO Supply Voltages from 1.2V to 3.3V and SPC/SPD format such as 16-bit 5:6:5, 18-bit 6:6:6 or 24-bit 8:8:8
Supply Voltages from 1.8V to 3.3V.
enters through the device’s 24-bit bus. In YCrCb format,
Programmable power management
either 24-bit 4:4:4 data or 16-bit 4:2:2 is supported by the
Device fully programmable through serial port or can CH7034B’s color space converter. The device’s video
automatically load firmware from Chrontel Boot capture block also has an option to support 80/86 MPU
ROM (CH9904)
Offered in a 88-pin QFN package
interface. The input video signal can be either interlaced
or non-interlaced data formats.
201-1000-028 Rev. 1.22 11/19/2013
With its embedded high speed SDRAM, the CH7034B
can help manufactures design their products to achieve
simultaneous LVDS and HDTV/VGA display. Thanks to
the sophisticated scaler, the input LCD data with low
resolution or reduced-frame rate can be covert to high
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CH7034B pdf
CHRONTEL
CH7034B
1.2 Pin Description
Table 1: Pin Name Descriptions (QFN88 pin Package)
Pin #
1~6,8,
12~21,
25~29,
87~88,
7
Type
In
In
31,32
34,35
36,37
39,40
48
Out
Out
Out
Out
Out
49 Out
50 N/A
54 In
55 In/out
56 Out
Symbol
D[23:0]
RESETB
LLC*,LLC[1]
LDC0*,LDC0[1]
LDC1*,LDC1[1]
LDC2*,LDC2[1]
HSO/CSYNC
VSO
RESERVED
SPC
SPD
PWM
Description
Data Input
These pins accept 24 data input lines from a digital video port of a
graphics controller. The swing is defined by VDDIO.
All the unused data input pins should be pulled low with 10 K
resistors or shorted to Ground directly.
Reset Input
When this pin is low, the device is held in the power-on reset status.
When this pin is high, reset is controlled through the serial port.
LVDS Clock Outputs
These pins provide the differential clock output for the LVDS.
LVDS Data Channel 0 Outputs
These pins provide the LVDS differential outputs for data channel 0.
LVDS Data Channel 1 Outputs
These pins provide the LVDS differential outputs for data channel 1.
LVDS Data Channel 2 Outputs
These pins provide the LVDS differential outputs for data channel 2.
Horizontal sync signal output
The amplitude of this pin is from 0 to AVDD.
It also functions as a Composite sync output
Vertical sync signal output
The amplitude of this pin is from 0 to AVDD.
Reserved
This pin should be left open or pulled low with a 10 Kresistor in the
application.
Serial Port Clock Input
This pin functions as the clock pin of the serial port. External pull-up
6.8 Kresister is required.
Serial Port Data Input / Output
This pin functions as the bi-directional data pin of the serial port.
External pull-up 6.8 Kresister is required.
Backlight brightness adjustment
57
Out
ENAVDD
Panel Power Enable
Enable LCD panel VDD
58
Out
ENABLK
Back Light Enable
Enable back light of LCD panel
63 Out DDC_SC Routed Serial Port Clock Output to DDC
This pin functions as the clock bus of the serial port to DDC receiver.
This pin will require a pull-up resistor to the desired voltage level. A
pull-low resistor 10 Kto ground if unused.
64
In/out
DDC_SD
Routed Serial Port Data to DDC
This pin functions as the bi-directional data pin of the serial port to
DDC receiver. This pin will require a pull-up resistor to the desired
voltage level. A pull-low resistor 10 Kto ground if unused
65
In/ out
GPIO
General Purpose Input Output
67 Out XO
68 In
XI/FIN
Crystal Output
A parallel resonance crystal should be attached between this pin and
XI/FIN. However, if an external CMOS clock is attached to XI/FIN,
XO should be left open.
Crystal Input / External Reference Input
A parallel resonance crystal should be attached between this pin and
201-1000-028 Rev. 1.22 11/19/2013
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