|
|
PDF IDT82V3910 Data sheet ( Hoja de datos )
| Número de pieza | IDT82V3910 | |
| Descripción | Synchronous Ethernet SETS | |
| Fabricantes | Integrated Device Technology | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de IDT82V3910 (archivo pdf) en la parte inferior de esta página. Total 13 Páginas | ||
|
No Preview Available !
Synchronous Ethernet SETS
for 10GbE and 40GbE
IDT82V3910
Short Form Datasheet
FEATURES
HIGHLIGHTS
• Jitter generation <0.3 ps RMS (10 kHz to 20 MHz), meets jitter gen-
eration requirements of leading PHYs supporting 10GBASE-R,
10GBASE-W, 40GBASE-R, OC-192 and STM-64
• Features 0.5 mHz to 35 Hz bandwidth
• Provides node clock for ITU-T G.8261/G.8262 Synchronous Ether-
net (SyncE)
• Provides node clocks for Cellular and WLL base-station (GSM and
3G networks)
• Provides clocks for DSL access concentrators (DSLAM), especially
for Japan TCM-ISDN network timing based ADSL equipments
• Provides clocks for 1 Gigabit, 10 Gigabit, and 40 Gigabit Ethernet
• Supports clock generation for IEEE-1588 applications
MAIN FEATURES
• Provides an integrated solution for Synchronous Equipment Timing
Source, including Stratum 3, SMC, EEC-Option 1 and EEC-
Option 2 Clocks
• Integrates T4 DPLL and T0 DPLL; T4 DPLL locks independently or
locks to T0 DPLL
• Supports programmable DPLL bandwidth (0.5 mHz to 35 Hz) and
damping factor (1.2 to 20 in 5 steps)
• Supports 1.1X10-5 ppm absolute holdover accuracy and
4.4X10-8 ppm instantaneous holdover accuracy
• Supports hitless reference switching to minimize phase transients
on T0 DPLL output to be no more than 0.61 ns
• Integrates 2 jitter attenuating APLLs to generate ultra-low jitter
clocks
• Supports 3 clock modes: SONET, Ethernet, and Ethernet LAN-
PHY
• Supports up to two crystal connections, allowing each APLL to
support up to two modes of operation
• Supports input and output clocks whose frequencies range from
1PPS to 644.53125 MHz
• Includes 1PPS clock input and output
• Provides IN1 and IN2 for 64 kHz + 8 kHz or
64 kHz + 8 kHz + 0.4 kHz composite clocks
• Provides IN3, IN4, IN7~IN14 input CMOS clocks whose frequen-
cies range from 1PPS to 156.25 MHz
• Provides IN5 and IN6 input differential clocks whose frequencies
range from 1PPS to 625 MHz
• Provides OUT1 to OUT5 output CMOS clocks whose frequency
cover from 1PPS to 125 MHz
• Provides OUT6,OUT7,OUT10 and OUT11 output differential
clocks whose frequency cover from 25 MHz to 644.53125 MHz
• Provides OUT8 for composite clocks and OUT9 for 1.544 MHz/
2.048 MHz (BITS/SSU)
• Provides output clocks for BITS, GPS, 3G, GSM, etc.
• Provides a 1PPS, 2 kHz, 4 kHz, or 8 kHz frame sync input signal,
and a 1PPS, 2 kHz or 8 kHz frame sync output signal
• Internal DCO can be controlled by an external processor to be used
for IEEE-1588 clock generation
• Supports programmable input-to-output phase offset adjustment
• Limits the phase and frequency offset of the outputs
• Supports Forced or Automatic operating mode switch controlled by
an internal state machine. Automatic mode switch supports Free-
Run, Locked and Holdover modes
• Supports manual and automatic selected input clock switch
• Supports automatic hitless selected input clock switch on clock fail-
ure
• Supports three types of input clock sources: recovered clock from
STM-N or OC-n, PDH network synchronization timing and external
synchronization reference timing
• Supports AMI, LVPECL/LVDS and CMOS input/output technologies
• Supports Master/Slave application (two chips used together) to
enable system protection against single chip failure
• Supports Telcordia GR-1244-CORE, Telcordia GR-253-CORE,
ITU-T G.812, ITU-T G.8262, ITU-T G.813 and ITU-T G.783 Recom-
mendations
OTHER FEATURES
• I2C Microprocessor interface
• IEEE 1149.1 JTAG Boundary Scan
• Single 3.3 V operation with 5 V tolerant CMOS I/Os
• 1mm ball pitch CABGA green package
APPLICATIONS
• SMC / SEC (SONET / SDH equipment)
• EEC (Synchronous Ethernet equipment)
• Core and access IP switches / routers
• Gigabit and Terabit IP switches / routers
• Cellular and WLL base-station node clocks
• Broadband and multi-service access equipment
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.
2013 Integrated Device Technology, Inc.
1
July 1, 2013
DSC-7238/-
1 page  
IDT82V3910 SHORT FORM DATASHEET
SYNCHRONOUS ETHERNET SETS FOR 10GBE AND 40GBE
2 PIN DESCRIPTION
Table 1: Pin Description
Name
Pin No.
I/O
OSCI
A11
I
FF_SRCSW
A10
I pull-down
MS/SL
D6 I pull-up
SONET/SDH
E6
I pull-down
RST H13 I pull-up
EX_SYNC1
EX_SYNC2
F11
G11
IN1 A7
IN2 B7
IN3 H14
I pull-down
I pull-down
I
I
I pull-down
Type Description 1
Global Control Signal
CMOS
CMOS
OSCI: Crystal Oscillator Master Clock
A nominal 12.8000 MHz clock provided by a crystal oscillator is input on this pin. It is the
master clock for the device.
FF_SRCSW: External Fast Selection Enable
During reset, this pin determines the default value of the EXT_SW bit (b4,
MON_SW_HS_CNFG). The EXT_SW bit determines whether the External Fast Selection is
enabled.
High: The default value of the EXT_SW bit (b4, MON_SW_HS_CNFG) is ‘1’ (External Fast
selection is enabled);
Low: The default value of the EXT_SW bit (b4, MON_SW_HS_CNFG) is ‘0’ (External Fast
selection is disabled).
After reset, this pin selects an input clock pair for the T0 DPLL if the External Fast selection
is enabled:
High: Pair IN3 / IN5 is selected.
Low: Pair IN4 / IN6 is selected.
After reset, the input on this pin takes no effect if the External Fast selection is disabled.
CMOS
MS/SL: Master / Slave Selection
This pin, together with the MS_SL_CTRL bit (b0, MS_SL_CTRL_CNFG), controls whether
the device is configured as the Master or as the Slave. Refer to Chapter 3.14 Master / Slave
Configuration for details.
The signal level on this pin is reflected by the MASTER_SLAVE bit (b1, INPUT_-
MODE_CNFG).
High: The value of the MASTER_SLAVE bit is ‘1’
Low: The value of the MASTER_SLAVE bit is ‘0’
CMOS
SONET/SDH: SONET / SDH Frequency Selection
During reset, this pin determines the default value of the IN_SONET_SDH bit (b2, INPUT_-
MODE_CNFG):
High: The default value of the IN_SONET_SDH bit is ‘1’ (SONET);
Low: The default value of the IN_SONET_SDH bit is ‘0’ (SDH).
After reset, the value on this pin takes no effect.
CMOS
RST: Reset
A low pulse of at least 50 µs on this pin resets the device. After this pin is high, the device
will still be held in reset state for 500 ms (typical).
Frame Synchronization Input Signal
CMOS
CMOS
EX_SYNC1: External Sync Input 1
A 2 kHz, 4 kHz, 8 kHz, or 1PPS signal is input on this pin.
EX_SYNC2: External Sync Input 1
A 2 kHz, 4 kHz, 8 kHz, or 1PPS signal is input on this pin.
Input Clock
AMI
AMI
CMOS
IN1: Input Clock 1
A 64 kHz + 8 kHz or 64 kHz + 8 kHz + 0.4 kHz composite clock is input on this pin.
IN2: Input Clock 2
A 64 kHz + 8 kHz or 64 kHz + 8 kHz + 0.4 kHz composite clock is input on this pin.
IN3: Input Clock 3
A 1 PPS, 2 kHz, 4 kHz, N x 8 kHz 3, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.25 MHz,
6.48 MHz, 10MHz, 19.44 MHz, 25MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz,
125MHz, 155.52 MHz or 156.25 MHz clock is input on this pin.
Pin Description
5
July 1, 2013
5 Page 
IDT82V3910 SHORT FORM DATASHEET
SYNCHRONOUS ETHERNET SETS FOR 10GBE AND 40GBE
2.1 RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
2.1.1 INPUTS
Control Pins
All control pins have internal pull-ups or pull-downs; additional resis-
tance is not required but can be added for additional protection. A 1kΩ
resistor can be used.
Single-Ended Clock Inputs
For protection, unused single-ended clock inputs should be tied to
ground.
Differential Clock Inputs
For applications not requiring the use of a differential input, both
*_POS and *_NEG can be left floating. Though not required, but for
additional protection, a 1kΩ resistor can be tied from _POS to ground.
XTAL Inputs
For applications not requiring the use of a crystal oscillator input,
both _IN and _OUT can be left floating. Though not required, but for
additional protection, a 1kΩ resistor can be tied from _IN to ground.
2.1.2 OUTPUTS
Status Pins
For applications not requiring the use of a status pin, we recommend
bringingouttoatestpointfordebuggingpurposes.
Single-Ended Clock Outputs
All unused single-ended clock outputs can be left floating, or can be
broughtouttoatestpointfordebuggingpurposes.
Differential Clock Outputs
All unused differential outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output pair
should either be left floating or terminated.
Recommendations for Unused Input and Output Pins
11
July 1, 2013
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet IDT82V3910.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| IDT82V3910 | Synchronous Ethernet SETS | Integrated Device Technology |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |