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PDF ICS87974I Data sheet ( Hoja de datos )

Número de pieza ICS87974I
Descripción LVCMOS/LVTTL CLOCK GENERATOR
Fabricantes Integrated Device Technology 
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ICS87974I
LOW SKEW, 1-TO-15,
LVCMOS/LVTTL CLOCK GENERATOR
GENERAL DESCRIPTION
The ICS87974I is a low skew, low jitter 1-to-15 LVCMOS/
LVTTL Clock Generator/Zero Delay Buffer. The device has
a fully integrated PLL and three banks whose divider ratios
can be independently controlled, providing output
frequency relationships of 1:1, 2:1, 3:1, 3:2, 3:2:1. In
addition, the external feedback connection provides for a
wide selection of output-to-input frequency ratios. The CLK0
and CLK1 pins allow for redundant clocking on the input
and dynamically switching the PLL between two clock
sources.
Guaranteed low jitter and output skew characteristics make
the ICS87974I ideal for those applications demanding well
defined performance and repeatability.
FEATURES
Fully integrated PLL
Fifteen single ended 3.3V LVCMOS/LVTTL outputs
Two LVCMOS/LVTTL clock inputs for redundant clock
applications
CLK0 and CLK1 accepts the following input levels:
LVCMOS/LVTTL
Output frequency range: 8.33MHz to 125MHz
VCO range: 200MHz to 500MHz
External feedback for ”zero delay” clock regeneration
Cycle-to-cycle jitter: ±100ps (typical)
Output skew: 350ps (maximum)
3.3V operating supply
-40°C to 85°C ambient operating temperature
Available in both standard and lead-free RoHS-compliant
packages
PIN ASSIGNMENT
GND
nMR/OE
CLK_EN
SEL_B
SEL_C
PLL_SEL
SEL_A
CLK_SEL
CLK0
CLK1
nc
VDD
VDDA
52 51 50 49 48 47 46 45 44 43 42 41 40
1 39
2 38
3 37
4 36
5 35
6 34
7
ICS87974I
33
8 32
9 31
10 30
11 29
12 28
13 27
14 15 16 17 18 19 20 21 22 23 24 25 26
GND
QB1
VDDOB
QB2
GND
QB3
VDDOB
QB4
FB_IN
GND
QFB
VDDOFB
nc
52-Lead LQFP
10mm x 10mm x 1.4mm package body
Y package
Top View
87974CYI
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1
REV. E JULY 26, 2010

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ICS87974I pdf
ICS87974I
LOW SKEW, 1-TO-15,
LVCMOS/LVTTL CLOCK GENERATOR
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
Test Conditions
CIN
RPULLUP
RPULLDOWN
CPD
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Power Dissipation Capacitance
(per output); Note 1
VDD, VDDA, VDDOx = 3.465V
ROUT
Output Impedance
NOTE 1: VDDOx denotes VDDOA, VDDOB, VDDOC, VDDOFB.
Minimum
Typical
4
51
51
Maximum
Units
pF
KΩ
KΩ
15 pF
5 7 12 Ω
TABLE 3A. OUTPUT CONTROL PIN FUNCTION TABLE
Inputs
nMR/OE
CLK_EN
0X
10
11
QA0:QA4
HiZ
LOW
Enable
Outputs
QB0:QB4
QC0:QC3
HiZ HiZ
LOW
LOW
Enable
Enable
QFB
HiZ
Enable
Enable
TABLE 3B. OPERATING MODE FUNCTION TABLE
Inputs
PLL_SEL
0
1
Operating Mode
Bypass
PLL
TABLE 3C. PLL INPUT FUNCTION TABLE
Inputs
CLK_SEL
PLL Input
0 CLK0
1 CLK1
TABLE 3D. SELECT PIN FUNCTION TABLE
SEL_A
0
1
QAx
÷2
÷4
SEL_B
0
1
QBx
÷2
÷4
SEL_C
0
1
QCx
÷4
÷6
TABLE 3E. FB SELECT FUNCTION TABLE
Inputs
FB_SEL1
FB_SEL0
00
10
01
11
Outputs
QFB
÷4
÷6
÷8
÷ 12
TABLE 3F. VCO SELECT FUNCTION TABLE
Inputs
VCO_SEL
fVCO
0 VCO/2
1 VCO/4
87974CYI
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REV. E JULY 26, 2010

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ICS87974I arduino
ICS87974I
LOW SKEW, 1-TO-15,
LVCMOS/LVTTL CLOCK GENERATOR
The following component footprints are used in this layout
example:
All the resistors and capacitors are size 0603.
POWER AND GROUNDING
Place the decoupling capacitors as close as possible to the power
pins. If space allows, placement of the decoupling capacitor on
the component side is preferred. This can reduce unwanted in-
ductance between the decoupling capacitor and the power pin
caused by the via.
Maximize the power and ground pad sizes and number of vias
capacitors. This can reduce the inductance between the power
and ground planes and the component power and ground pins.
The RC filter consisting of R7, C11, and C16 should be placed
as close to the VDDA pin as possible.
CLOCK TRACES AND TERMINATION
Poor signal integrity can degrade the system performance or
cause system failure. In synchronous high-speed digital systems,
the clock signal is less tolerant to poor signal integrity than other
signals. Any ringing on the rising or falling edge or excessive ring
back can cause system failure. The shape of the trace and the
trace delay might be restricted by the available space on the board
and the component location. While routing the traces, the clock
signal traces should be routed first and should be locked prior to
routing other signal traces.
• The differential 50Ω output traces should have same
length.
• Avoid sharp angles on the clock trace. Sharp angle
turns cause the characteristic impedance to change on
the transmission lines.
• Keep the clock traces on the same layer.Whenever pos-
sible, avoid placing vias on the clock traces. Placement
of vias on the traces can affect the trace characteristic
impedance and hence degrade signal integrity.
• To prevent cross talk, avoid routing other signal traces in
parallel with the clock traces. If running parallel traces is
unavoidable, allow a separation of at least three trace
widths between the differential clock trace and the other
signal trace.
• Make sure no other signal traces are routed between the
clock trace pair.
• The series termination resistors should be located as
close to the driver pins as possible.
Pin 1
U1
ICS87974
C12 C10
C9
C8
C7
GND
VDDO
VDD
VDDA
VIA
C13
R7 C16 C11
87974CYI
C3 C4
C6
C5
FIGURE 2B. PCB BOARD LAYOUT FOR ICS87974I
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REV. E JULY 26, 2010

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