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Número de pieza ICS854S054I
Descripción 4:1 Differential-to-LVDS Clock Multiplexer
Fabricantes Integrated Device Technology 
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4:1 Differential-to-LVDS Clock Multiplexer
ICS854S054I
DATA SHEET
General Description
The ICS854S054I is a 4:1 Differential-to-LVDS Clock Multiplexer
which can operate up to 2.5GHz. The ICS854S054I has 4 selectable
differential clock inputs. The PCLK, nPCLK input pairs can accept
LVPECL, LVDS or CML levels. The fully differential architecture and
low propagation delay make it ideal for use in clock distribution
circuits. The select pins have internal pulldown resistors. The SEL1
pin is the most significant bit and the binary number applied to the
select pins will select the same numbered data input (i.e., 00 selects
PCLK0, nPCLK0).
Features
High speed 4:1 differential multiplexer
One differential LVDS output pair
Four selectable differential PCLK, nPCLK input pairs
PCLKx, nPCLKx pairs can accept the following differential
input levels: LVPECL, LVDS, CML
Maximum output frequency: 2.5GHz
Translates any single ended input signal to LVDS levels with
resistor bias on nPCLKx input
Additive phase jitter, RMS: 0.147ps (typical)
Part-to-part skew: 300ps (maximum)
Propagation delay: 700ps (maximum)
Supply voltage range: 3.135V to 3.465V
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Block Diagram
PCLK0 Pulldown
nPCLK0 Pullup/Pulldown
PCLK1 Pulldown
nPCLK1 Pullup/Pulldown
PCLK2 Pulldown
nPCLK2 Pullup/Pulldown
PCLK3 Pulldown
nPCLK3 Pullup/Pulldown
00 (default)
01
10
11
SEL1 Pulldown
SEL0 Pulldown
ICS854S054AGI REVISION A SEPTEMBER 28, 2012
Pin Assignment
PCLK0
nPCLK0
PCLK1
nPCLK1
VDD
SEL0
SEL1
GND
1
2
3
4
5
6
7
8
16 VDD
15 Q
14 nQ
13 GND
12 nPCLK3
11 PCLK3
10 nPCLK2
9 PCLK2
ICS854S054I
16-Lead TSSOP
Q 5.0mm x 4.4mm x 0.92mm package body
nQ G Package
Top View
1 ©2012 Integrated Device Technology, Inc.

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ICS854S054I pdf
ICS854S054I Data Sheet
4:1, DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER
Additive Phase Jitter
The spectral purity in a band at a specific offset from the fundamental
compared to the power of the fundamental is called the dBc Phase
Noise. This value is normally expressed using a Phase noise plot
and is most often the specified plot in many applications. Phase noise
is defined as the ratio of the noise power present in a 1Hz band at a
specified offset from the fundamental frequency to the power value of
the fundamental. This ratio is expressed in decibels (dBm) or a ratio
of the power in the 1Hz band to the power in the fundamental. When
the required offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the fundamental.
By investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the entire
time record of the signal. It is mathematically possible to calculate an
expected bit error rate given a phase noise plot.
Offset from Carrier Frequency (Hz)
As with most timing specifications, phase noise measurements has
issues relating to the limitations of the equipment. Often the noise
floor of the equipment is higher than the noise floor of the device. This
is illustrated above. The device meets the noise floor of what is
shown, but can actually be lower. The phase noise is dependent on
the input source and measurement equipment.
Measured using a Rohde & Schwarz SMA100 as the input source.
ICS854S054AGI REVISION A SEPTEMBER 28, 2012
5
©2012 Integrated Device Technology, Inc.

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ICS854S054I arduino
ICS854S054I Data Sheet
4:1, DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER
LVDS Power Considerations
This section provides information on power dissipation and junction temperature for the ICS854S054I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS854S054I is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
• Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 68mA = 235.62mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 100°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.236W * 100°C/W = 108.6°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 6. Thermal Resistance θJA for 16 Lead TSSOP, Forced Convection
θJA by Velocity
Meters per Second
0
Multi-Layer PCB, JEDEC Standard Test Boards
100°C/W
1
94.2°C/W
2.5
90.2°C/W
ICS854S054AGI REVISION A SEPTEMBER 28, 2012
11
©2012 Integrated Device Technology, Inc.

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