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PDF ICS853S310I Data sheet ( Hoja de datos )

Número de pieza ICS853S310I
Descripción 1-to-8 Differential-to- 3.3V LVPECL/ECL Fanout Buffer
Fabricantes Integrated Device Technology 
Logotipo Integrated Device Technology Logotipo



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Low Skew, 1-to-8 Differential-to-
3.3V LVPECL/ECL Fanout Buffer
ICS853S310I
DATA SHEET
General Description
The ICS853S310I is a low skew, high performance 1-to-8
Differential-to-3.3V LVPECL/ECL Fanout Buffer. The PCLKx,
nPCLKx pairs can accept LVPECL, LVDS, CML and SSTL
differential input levels. The ICS853S310I is characterized to operate
from a 3.3V power supply. Guaranteed output and part-to-part skew
characteristics make the ICS853S310I ideal for those clock
distribution applications demanding well defined performance and
repeatability.
Features
Eight differential 3.3V LVPECL/ECL outputs
Two selectable differential input pairs
PCLKx, nPCLKx pairs can accept the following
differential input levels: LVPECL, LVDS, CML, SSTL
Maximum output frequency: 2GHz
Translates any single-ended input signal to 3.3V LVPECL levels
with resistor bias on nPCLKx input
Output skew: 20ps (typical)
Propagation delay: 825ps (typical)
Additive phase jitter, RMS: 0.14ps (typical)
LVPECL mode operating voltage supply range:
VCC = 3.0V to 3.8V, VEE = 0V
ECL mode operating voltage supply range:
VCC = 0V, VEE = -3.0V to -3.8V
-40°C to 85°C ambient operating temperature
Available lead-free (RoHS 6) package
Block Diagram
PCLK0 Pulldown
nPCLK0 Pullup/Pulldown
PCLK1 Pulldown
nPCLK1 Pullup/Pulldown
0
1
CLK_SEL Pulldown
VBB
Pin Assignment
Q0
nQ0 25 24 23 22 21 20 19
Q1
VEE 26
18 Q3
nQ1 CLK_SEL 27
17 nQ3
Q2 PCLK0 28
16 Q4
nQ2
VCC 1
15 VCCO
Q3 nPCLK0 2
14 nQ4
nQ3
VBB 3
13 Q5
PCLK1 4
Q4
12 nQ5
5 6 7 8 9 10 11
nQ4
Q5
nQ5
ICS853S310I
Q6
nQ6 28-Lead PLCC
11.6mm x 11.4mm x 4.1mm package body
Q7 V Package
nQ7 Top View
ICS853S310CVI REVISION A NOVEMBER 17, 2010
1
©2010 Integrated Device Technology, Inc.

1 page




ICS853S310I pdf
ICS853S310I Data Sheet
LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-3.3V LVPECL/ECL FANOUT BUFFER
AC Electrical Characteristics
Table 4. AC Characteristics, VCC = VCCO = 3.0V to 3.8V, VEE = 0V; or VEE = -3.8V to -3.0V, VCC = VCCO = 0V;
TA = -40°C to 85°C
-40°C
25°C
85°C
Symbol Parameter
Min Typ Max Min Typ Max Min Typ Max
fOUT
tPD
tsk(o)
Output Frequency
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
222
550 750 975 600 825 1050 625 885 1150
20 40
20 40
20 40
tsk(pp) Part-to-Part Skew; NOTE 3, 4 275 275 320
Buffer Additive Phase Jitter,
tjit RMS; refer to Additive Phase
Jitter Section
0.14
tR / tF
Output
Rise/Fall Time
20% to 80%
90
375 90
375 80
400
Units
GHz
ps
ps
ps
ps
ps
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE: All parameters are measured at fOUT 1.2GHz, unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential
cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency and
with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
ICS853S310CVI REVISION A NOVEMBER 17, 2010
5
©2010 Integrated Device Technology, Inc.

5 Page





ICS853S310I arduino
ICS853S310I Data Sheet
LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-3.3V LVPECL/ECL FANOUT BUFFER
Schematic Example
Figure 5A shows a schematic example of the ICS853S310I. In this
example, the PCLK0, nPCLK0 input is selected. The decoupling
capacitors should be physically located near the power pin. For
ICS853S310I, the unused outputs can be left floating.
VCC
Zo = 50 Ohm
Zo = 50 Ohm
LVPECL Driv er
R9
50
C5 (Option)
0.1u
U1
VCC
26
27
28
1
2
3
4
VEE
CLK_SEL
PCLK0
VCC
nPCLK0
VBB
PCLK1
R10 R3
50 1K
ICS853310
R11
50
(U1-8)
VCC
C1
0.1uF
VCC=3.3V
(U1-15) (U1-22) (U1-1)
C2
0.1uF
C3
0.1uF
C4
0.1uF
3.3V
Q3
nQ3
Q4
VCCO
nQ4
Q5
nQ5
18
17
16
15
14
13
12
Zo = 50
Zo = 50
+
-
R2 R1
50 50
C6 (Option)
0.1u
R3
50
Zo = 50
Zo = 50
+
-
R8 R7
50 50
C7 (Option)
0.1u
R13
50
Figure 5A. ICS853S310I LVPECL Clock Output Buffer Schematic Example
ICS853S310CVI REVISION A NOVEMBER 17, 2010
11
©2010 Integrated Device Technology, Inc.

11 Page







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