DataSheet.es    


PDF 5P49V5908 Data sheet ( Hoja de datos )

Número de pieza 5P49V5908
Descripción Programmable Clock Generator
Fabricantes Integrated Device Technology 
Logotipo Integrated Device Technology Logotipo



Hay una vista previa y un enlace de descarga de 5P49V5908 (archivo pdf) en la parte inferior de esta página.


Total 30 Páginas

No Preview Available ! 5P49V5908 Hoja de datos, Descripción, Manual

Programmable Clock Generator
5P49V5908
Description
The 5P49V5908 is a programmable clock generator intended
for high performance consumer, networking, industrial,
computing, and data-communications applications.
Configurations may be stored in on-chip One-Time
Programmable (OTP) memory or changed using I2C
interface. This is IDTs fifth generation of programmable clock
technology (VersaClock® 5).
The frequencies are generated from a single reference clock
or crystal. Two select pins allow up to 4 different
configurations to be programmed and accessible using
processor GPIOs or bootstrapping. The different selections
may be used for different operating modes (full function,
partial function, partial power-down), regional standards (US,
Japan, Europe) or system production margin testing.
The device may be configured to use one of two I2C
addresses to allow multiple devices to be used in a system.
Pin Assignment
OUT10B
XOUT
XIN/REF
VDDA
VDDO
OUT9
OUT9B
OUT8
OUT8B
OUT7
OUT7B
SD/OE
48 47 46 45 44 43 42 41 40 39 38 37
1 36
2 35
3 34
4 33
5 32
6 31
EPAD
7 30
8 29
9 28
10 27
11 26
12 25
13 14 15 16 17 18 19 20 21 22 23 24
VDDO2
OUT2
OUT2B
OEB7_10
NC
VDD
VDD_CORE
OUT3
OUT3B
VDDO
NC
NC
48-pin VFQFPN
DATASHEET
Features
Generates up to four independent output frequencies with a
total of 11 differential outputs and one reference output
Supports multiple differential output I/O standards:
– Three universal outputs pairs with each configurable
as one differential output pair (LVDS, LVPECL or
regular HCSL) or two LVCMOS outputs. Frequency
of each output pair can be individually programmed
– Eight copies of Low Power HCSL(LP-HCSL) outputs.
Programmable frequency
– See Output Features and Descriptions for details
One reference LVCMOS output clock
High performance, low phase noise PLL, <0.7 ps RMS
typical phase jitter on outputs:
– PCIe Gen1, 2, 3 compliant clock capability
– USB 3.0 compliant clock capability
– 1 GbE and 10 GbE
Four fractional output dividers (FODs)
Independent Spread Spectrum capability from each
fractional output divider (FOD)
Four banks of internal non-volatile in-system
programmable or factory programmable OTP memory
I2C serial programming interface
Input frequency ranges:
– LVCMOS Reference Clock Input (XIN/REF) – 1MHz
to 200MHz
– Crystal frequency range: 8MHz to 40MHz
Output frequency ranges:
– LVCMOS Clock Outputs – 1MHz to 200MHz
– LP-HCSL Clock Outputs – 1MHz to 200MHz
– Other Differential Clock Outputs – 1MHz to 350MHz
Programmable loop bandwidth
Programmable crystal load capacitance
Power-down mode
Mixed voltage operation:
– 1.8V core
– 1.8V VDDO for 8 LP-HCSL outputs
– 1.8V to 3.3V VDDO for other outputs
(3 programmable differential outputs and 1 reference
output)
– See Pin Descriptions for details
Available in 48-pin VFQFPN package (NDG48)
-40° to +85°C industrial temperature operation
5P49V5908 NOVEMBER 11, 2016
1 ©2015 Integrated Device Technology, Inc.

1 page




5P49V5908 pdf
5P49V5908 DATASHEET
Crystal Input (XIN/REF)
The crystal used should be a fundamental mode quartz
crystal; overtone crystals should not be used.
A crystal manufacturer will calibrate its crystals to the nominal
frequency with a certain load capacitance value. When the
oscillator load capacitance matches the crystal load
capacitance, the oscillation frequency will be accurate. When
the oscillator load capacitance is lower than the crystal load
capacitance, the oscillation frequency will be higher than
nominal and vice versa so for an accurate oscillation
frequency you need to make sure to match the oscillator load
capacitance with the crystal load capacitance.
To set the oscillator load capacitance there are two tuning
capacitors in the IC, one at XIN and one at XOUT. They can
be adjusted independently but commonly the same value is
used for both capacitors. The value of each capacitor is
composed of a fixed capacitance amount plus a variable
capacitance amount set with the XTAL[5:0] register.
Adjustment of the crystal tuning capacitors allows for
maximum flexibility to accommodate crystals from various
manufacturers. The range of tuning capacitor values available
are in accordance with the following table.
XTAL[5:0] Tuning Capacitor Characteristics
Parameter
XTAL
Bits Step (pF) Min (pF)
6 0.5
9
Max (pF)
25
The capacitance at each crystal pin inside the chip starts at
9pF with setting 000000b and can be increased up to 25pF
with setting 111111b. The step per bit is 0.5pF.
You can write the following equation for this capacitance:
Ci = 9pF + 0.5pF × XTAL[5:0]
The PCB where the IC and the crystal will be assembled adds
some stray capacitance to each crystal pin and more
capacitance can be added to each crystal pin with additional
external capacitors.
You can write the following equations for the total capacitance
at each crystal pin:
CXIN = Ci1 + Cs1 + Ce1
CXOUT = Ci2 + Cs2 + Ce2
Ci1 and Ci2 are the internal, tunable capacitors. Cs1 and Cs2
are stray capacitances at each crystal pin and typical values
are between 1pF and 3pF.
Ce1 and Ce2 are additional external capacitors that can be
added to increase the crystal load capacitance beyond the
tuning range of the internal capacitors. However, increasing
the load capacitance reduces the oscillator gain so please
consult the factory when adding Ce1 and/or Ce2 to avoid
crystal startup issues. Ce1 and Ce2 can also be used to adjust
for unpredictable stray capacitance in the PCB.
The final load capacitance of the crystal:
CL = CXIN × CXOUT / (CXIN + CXOUT)
For most cases it is recommended to set the value for
capacitors the same at each crystal pin:
CXIN = CXOUT = Cx CL = Cx / 2
The complete formula when the capacitance at both crystal
pins is the same:
CL = (9pF + 0.5pF × XTAL[5:0] + Cs + Ce) / 2
Example 1: The crystal load capacitance is specified as 8pF
and the stray capacitance at each crystal pin is Cs=1.5pF.
Assuming equal capacitance value at XIN and XOUT, the
equation is as follows:
8pF = (9pF + 0.5pF × XTAL[5:0] + 1.5pF) / 2
0.5pF × XTAL[5:0] = 5.5pF XTAL[5:0] = 11 (decimal)
Example 2: The crystal load capacitance is specified as 12pF
and the stray capacitance Cs is unknown. Footprints for
external capacitors Ce are added and a worst case Cs of 5pF
is used. For now we use Cs + Ce = 5pF and the right value for
Ce can be determined later to make 5pF together with Cs.
12pF = (9pF + 0.5pF × XTAL[5:0] + 5pF) / 2
XTAL[5:0] = 20 (decimal)
NOVEMBER 11, 2016
 
5
PROGRAMMABLE CLOCK GENERATOR

5 Page





5P49V5908 arduino
5P49V5908 DATASHEET
Table 10:Crystal Characteristics
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Load Capacitance (CL) @ <=25 MHz
Load Capacitance (CL) >25M to 40M
Maximum Crystal Drive Level
Test Conditions
Minimum Typical Maximum
Fundamental
8 25 40
10 100
7
6 8 12
68
100
Units
MHz
pF
pF
pF
µW
Note: Typical crystal used is FOX 603-25-150. For different reference crystal options please go to www.foxonline.com.
Table 11: DC Electrical Characteristics
Symbol
Iddcore3
Parameter
Core Supply Current
Test Conditions
100 MHz on all outputs, 25 MHz
REFCLK
Min Typ Max Unit
44 mA
LVPECL, 350 MHz, 3.3V VDDOx
42 47 mA
LVPECL, 350 MHz, 2.5V VDDOx
37 42 mA
LVDS, 350 MHz, 3.3V VDDOx
18 21 mA
LVDS, 350 MHz, 2.5V VDDOx
17 20 mA
LVDS, 350 MHz, 1.8V VDDOx
16 19 mA
HCSL, 250 MHz, 3.3V VDDOx, 2 pF load
29 33 mA
Iddox
Output Buffer Supply Current
HCSL, 250 MHz, 2.5V VDDOx, 2 pF load
LVCMOS, 50 MHz, 3.3V, VDDOx 1,2
LVCMOS, 50 MHz, 2.5V, VDDOx 1,2
LVCMOS, 50 MHz, 1.8V, VDDOx 1,2
LVCMOS, 200 MHz, 3.3V VDDOx1
LVCMOS, 200 MHz, 2.5V VDDOx1,2
LVCMOS, 200 MHz, 1.8V VDDOx1,2
28 33 mA
16 18 mA
14 16 mA
12 14 mA
36 42 mA
27 32 mA
16 19 mA
Iddpd
Power Down Current
SD asserted, I2C Programming
10 14 mA
1. Single CMOS driver active.
2. Measured into a 5” 50 Ohm trace with 2 pF load.
3. Iddcore = IddA+ IddD, no loads.
Outputs Features and Descriptions
OUT1/OUT1B, OUT2/OUT2B, and OUT4/OUT4B can form three output pairs. Each output pair has individually programmable
frequencies and can be configured as one differential pair (LVDS, LVPECL, regular HCSL) or two LVCMOS outputs. VDDO is
individually selectable from 1.8V to 3.3V for LVDS and LVCMOS, and 2.5V to 3.3V for LVPECL and regular current-mode HCSL
outputs.
OUT3, 5-11 are 8 Low-Power HCSL(LP-HCSL) differential output pairs. They are the same frequency which can be individually
programmed. They utilize the 1.8V LP-HCSL technology which can reduce supply current and termination resistor count.
LP-HCSL outputs are from 1MHz to 200MHz and other differential outputs are from 1MHz to 350MHz.
NOVEMBER 11, 2016
11 PROGRAMMABLE CLOCK GENERATOR

11 Page







PáginasTotal 30 Páginas
PDF Descargar[ Datasheet 5P49V5908.PDF ]




Hoja de datos destacado

Número de piezaDescripciónFabricantes
5P49V5901Programmable Clock GeneratorIntegrated Device Technology
Integrated Device Technology
5P49V5907Programmable Clock GeneratorIntegrated Device Technology
Integrated Device Technology
5P49V5908Programmable Clock GeneratorIntegrated Device Technology
Integrated Device Technology

Número de piezaDescripciónFabricantes
SLA6805M

High Voltage 3 phase Motor Driver IC.

Sanken
Sanken
SDC1742

12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.

Analog Devices
Analog Devices


DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.


DataSheet.es    |   2020   |  Privacy Policy  |  Contacto  |  Buscar