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PDF LE25S40AMC Data sheet ( Hoja de datos )
| Número de pieza | LE25S40AMC | |
| Descripción | 4M-bit (512K x 8) Serial Flash Memory | |
| Fabricantes | ON Semiconductor | |
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LE25S40AMC
CMOS LSI
4M-bit (512K x 8)
Serial Flash Memory
www.onsemi.com
Overview
The LE25S40A is a SPI bus flash memory device with a 4M bit (512K
8-bit) configuration that adds a high performance Dual output and Dual I/O
function. It uses a single 1.8V power supply. While making the most of the
features inherent to a serial flash memory device, the LE25S40A is housed in
an 8-pin ultra-miniature package. All these features make this device ideally
suited to storing program in applications such as portable information
devices, which are required to have increasingly more compact dimensions.
The LE25S40A also has a small sector erase capability which makes the
device ideal for storing parameters or data that have fewer rewrite cycles and
conventional EEPROMs cannot handle due to insufficient capacity.
SOP8J(200mil)
Function
Read/write operations enabled by single 1.8V power supply : 1.65 to 1.95V supply voltage range
Operating frequency
: 40MHz
Temperature range
: –40 to +90C
Serial interface
: SPI mode 0, mode 3 supported
Sector size
: 4K bytes/small sector, 64K bytes/sector
Small sector erase, sector erase, chip erase functions
Page program function (256 bytes / page)
Block protect function
Data retention period
: 20 years
Status functions
: Ready/busy information, protect information
Highly reliable read/write
Number of rewrite times : 100,000 times
Small sector erase time : 40ms (typ.), 150ms (max.)
Sector erase time
: 80ms (typ.), 250ms (max.)
Chip erase time
: 400ms (typ.), 4.0s (max.)
Page program time
: 0.8ms/256 bytes (typ.), 1.0ms/256 bytes (max.)
Package
: SOP8J / SOIC-8, CASE 751CU
* This product is licensed from Silicon Storage Technology, Inc. (USA).
ORDERING INFORMATION
See detailed ordering and shipping information on page 23 of this data sheet.
© Semiconductor Components Industries, LLC, 2014
November 2014 - Rev. 2
1
Publication Order Number :
LE25S40AMC/D
1 page  
Figure 1. Pin Assignments
LE25S40AMC
CS
SO/SIO1
WP
VSS
18
27
36
45
Top view
VDD
HOLD
SCK
SI/SIO0
Table 1. Pin Description
Symbol
Pin Name
SCK
Serial clock
SI/SIO0
SO/SIO1
CS
Serial data input
/ Serial data input output
Serial data input
/ Serial data input output
Chip select
WP
HOLD
VDD
VSS
Write protect
Hold
Power supply
Ground
Figure 2. Block Diagram
Description
This pin controls the data input/output timing.
The input data and addresses are latched synchronized to the rising edge of the serial clock, and the data is
output synchronized to the falling edge of the serial clock.
The data and addresses are input from this pin, and latched internally synchronized to the rising edge of the
serial clock. It changes into the output pin at Dual Output and it changes into the input output pin at Dual I/O.
The data stored inside the device is output from this pin synchronized to the falling edge of the serial clock. It
changes into the output pin at Dual Output and it changes into the input output pin at Dual I/O.
The device becomes active when the logic level of this pin is low; it is deselected and placed in standby status
when the logic level of the pin is high.
The status register write protect (SRWP) takes effect when the logic level of this pin is low.
Serial communication is suspended when the logic level of this pin is low.
This pin supplies the 1.65 to 1.95V supply voltage.
This pin supplies the 0V supply voltage.
ADDRESS
BUFFERS
&
LATCHES
X-
DECODER
4M Bit
Flash EEPROM
Cell Array
Y-DECODER
CONTROL
LOGIC
I/O BUFFERS
&
DATA LATCHES
SERIAL INTERFACE
CS SCK SI/SIO0 SO/SIO1 WP HOLD
www.onsemi.com
5
5 Page 
LE25S40AMC
3-2. Status register write
The information in status registers BP0, BP1, BP2, TB and SRWP can be rewritten using the status register write
command. RDY, WEN and bit 6 are read-only bits and cannot be rewritten. The information in bits BP0, BP1, BP2, TB
and SRWP is stored in the non-volatile memory, and when it is written in these bits, the contents are retained even at
power-down. "Figure 7 Status Register Write" shows the timing waveforms of status register write, and Figure 20
shows a status register write flowchart. Consisting of the first and second bus cycles, the status register write command
initiates the internal write operation at the rising CS edge after the data has been input following (01h). Erase and
program are performed automatically inside the device by status register write so that erasing or other processing is
unnecessary before executing the command. By the operation of this command, the information in bits BP0, BP1, BP2,
TB and SRWP can be rewritten. Since bits RDY (bit 0), WEN (bit 1) and bit 6 of the status register cannot be written, no
problem will arise if an attempt is made to set them to any value when rewriting the status register. Status register write
ends can be detected by RDY of status register read. To initiate status register write, the logic level of the WP pin must
be set high and status register WEN must be set to "1".
Figure 7. Status Register Write
CS tWPS
Self-timed
Write Cycle
tSRW
tWPH
WP
SCK
SI
SO
Mode3
Mode0
0 1 2 3 4 5 6 7 8 15
MSB
8CLK
01h
DATA
High Impedance
3-3. Contents of each status register
RDY (Bit0)
The RDY register is for detecting the write (program, erase and status register write) end. When it is "1", the device is in
a busy state, and when it is "0", it means that write is completed.
WEN (Bit1)
The WEN register is for detecting whether the device can perform write operations. If it is set to "0", the device will not
perform the write operation even if the write command is input. If it is set to "1", the device can perform write
operations in any area that is not block-protected.
WEN can be controlled using the write enable and write disable commands. By inputting the write enable command
(06h), WEN can be set to "1"; by inputting the write disable command (04h), it can be set to "0." In the following states,
WEN is automatically set to "0" in order to protect against unintentional writing.
At power-on
Upon completion of small sector erase, sector erase or chip erase
Upon completion of page program
Upon completion of status register write
* If a write operation has not been performed inside the LE25S40A because, for instance, the command input for any of
the write operations (small sector erase, sector erase, chip erase, page program, or status register write) has failed or a
write operation has been performed for a protected address, WEN will retain the status established prior to the issue of
the command concerned. Furthermore, its state will not be changed by a read operation.
www.onsemi.com
11
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