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PDF LE25S81A Data sheet ( Hoja de datos )

Número de pieza LE25S81A
Descripción 8M-bit (1024K x 8) Serial Flash Memory
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LE25S81A
Serial Flash Memory
8M-bit (1024K x 8)
1. Overview
The LE25S81A is a SPI bus flash memory device with a 8M bit (1024K
× 8-bit) configuration. It uses a single power supply. While making the
most of the features inherent to a serial flash memory device, the
LE25S81A is housed in an 8-pin ultra-miniature package. All these
features make this device ideally suited to storing program in
applications such as portable information devices, which are required to
have increasingly more compact dimensions.
The LE25S81A also has a small sector erase capability which makes the
device ideal for storing parameters or data that have fewer rewrite cycles
and conventional EEPROMs cannot handle due to insufficient capacity.
www.onsemi.com
SOIC 8, 150 mils
VSOIC8 NB
2. Features
Operations power supply : 1.65 to 1.95V supply voltage range
Operating frequency
: 70MHz (max)
Temperature range
: –40 to +90°C
Serial interface
: SPI mode 0, mode 3 supported
Electronic Identification : JDEC ID, Device ID, Serial Flash Discoverable Parameter (SFDP)
Sector size
: 4K bytes/small sector, 64K bytes/sector
Erase functions
: small sector erase(SSE), sector erase(SE), chip erase(CHE)
Page program function
: 256 bytes/page
Status functions
: Ready/Busy information, protect information
Low operation current
: 5.0mA (Low-power program mode, typ), 3.0mA(Low-Power Read mode, typ)
Erase time
: 10ms(SSE, typ), 15ms(SE, typ), 120ms(CHE, typ)
Page program time (tPP) : 0.3ms/256 bytes (typ), 0.5ms/256 bytes (max)
Emergency shutdown of the current consumption
: transition to a standby state in less than 20us from the active by Write Suspend
: transition to a standby state in less than 40us from the active by Software Reset
High reliability
: 100,000 erase/program cycles
: 20 years data retention period
Package
: LE25S81AMD SOIC8, 150 mils
CASE 751BD-01
: LE25S81AFD VSOIC8 NB
CASE 753AA
: KGD
N/A
* This product is licensed from Silicon Storage Technology, Inc. (USA).
ORDERING INFORMATION
See detailed ordering and shipping information on page 51 of this data sheet.
© Semiconductor Components Industries, LLC, 2015
September 2015 - Rev. 3
1
Publication Order Number :
LE25S81A/D

1 page




LE25S81A pdf
5. Pin Description
Symbol
Pin Name
CS Chip select
SCK Serial clock
SI
(SIO0)
Serial data input
(Serial data input output)
SO
(SIO1)
Serial data output
(Serial data input output)
WP Write protect
HOLD Hold
NC No Connection
VDD
VSS
Power supply
Ground
LE25S81A
IO Description
The device becomes active when the logic level of this pin is low; it is deselected and placed in
I
standby status when the logic level of the pin is high.
This pin controls the data input/output timing.
I The input data and addresses are latched synchronized to the rising edge of the serial clock, and
the data is output synchronized to the falling edge of the serial clock.
The data and addresses are input from this pin, and latched internally synchronized to the rising
I/O edge of the serial clock.
(It changes into input/output pin during the Dual operation.)
The data stored inside the device is output from this pin synchronized to the falling edge of the
I/O serial clock.
( It changes into input/output pin during the Dual operation.)
I The Write Status Register Protect (SRWP) takes effect when the logic level of this pin is low.
I Serial communication is suspended when the logic level of this pin is low.
This pin supplies the 1.65 to 1.95V supply voltage.
This pin supplies the 0V supply voltage.
www.onsemi.com
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LE25S81A arduino
9-1. Contents of each status register
LE25S81A
9-1-1. RDY (bit 0)
The RDY register is for detecting the write (Program, Erase and Write Status Register) end. When it is "1", the device is in
a busy state, and when it is "0", it means that write is completed.
9-1-2. WEN (bit 1)
The WEN register is for detecting whether the device can perform write operations. If it is set to "0", the device will not
perform the write operation even if the write command is input. If it is set to "1", the device can perform write operations
in any area that is not block-protected.
WEN can be controlled using the write enable (WREN) and write disable (WRDI). By inputting the write enable (WREN:
06h), WEN can be set to "1" by inputting the write disable (WRDI: 04h), it can be set to "0." In the following states, WEN
is automatically set to "0" in order to protect against unintentional writing.
At power-on
Upon completion of Erase (SSE, SE, or CHE)
Upon completion of Page Program (PP or PPL)
Upon completion of Write Status Register (WRSR)
* If a write operation has not been performed inside the LE25S81A because, for instance, the command input for any of
the write operations (SSE, SE, CHE, PP, PPL or WRSR) has failed or a write operation has been performed for a
protected address, WEN will retain the status established prior to the issue of the command concerned. Furthermore, its
state will not be changed by a read operation.
9-1-3. BP0, BP1, BP2, TB (bits 2, 3, 4, 5)
Block Protect: BP0, BP1, BP2 and TB are status register bits that can be rewritten, and the memory space to be protected
can be set depending on these bits. For the setting conditions, refer to "Table 4. Protected Level Setting Conditions".
BP0, BP1, and BP2 are used to select the protected area and TB to allocate the protected area to the higher-order address
area or lower-order address area.
Table 4. Protection Level Setting Conditions
Protected Level
Protected Block
Status Register Bits
TB BP2 BP1
0
Whole area unprotected
X00
T1 Upper side 1/16 protected 0 0 0
T2
Upper side 1/8 protected
001
T3
Upper side 1/4 protected
001
T4
Upper side 1/2 protected
010
B1
Lower side 1/16 protected
10
0
B2
Lower side 1/8 protected
101
B3
Lower side 1/4 protected
101
B4
Lower side 1/2 protected
110
5
Whole area protected
X10
5
Whole area protected
X11
Note: Chip Erase is enabled only when the protection level is 0.
BP0
0
1
0
1
0
1
0
1
0
1
X
Protected Area
None
F0000h to FFFFFh
E0000h to FFFFFh
C0000h to FFFFFh
80000h to FFFFFh
00000h to 0FFFFh
00000h to 1FFFFh
00000h to 3FFFFh
00000h to 7FFFFh
00000h to FFFFFh
00000h to FFFFFh
www.onsemi.com
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