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PDF NCP5109B Data sheet ( Hoja de datos )

Número de pieza NCP5109B
Descripción High and Low Side Driver
Fabricantes ON Semiconductor 
Logotipo ON Semiconductor Logotipo



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No Preview Available ! NCP5109B Hoja de datos, Descripción, Manual

NCP5109A, NCP5109B
High Voltage, High and Low
Side Driver
The NCP5109 is a high voltage gate driver IC providing two
outputs for direct drive of 2 Nchannel power MOSFETs or IGBTs
arranged in a halfbridge configuration version B or any other
highside + lowside configuration version A.
It uses the bootstrap technique to ensure a proper drive of the
highside power switch. The driver works with 2 independent inputs.
Features
High Voltage Range: Up to 200 V
dV/dt Immunity ±50 V/nsec
Negative Current Injection Characterized Over the Temperature Range
Gate Drive Supply Range from 10 V to 20 V
High and Low Drive Outputs
Output Source / Sink Current Capability 250 mA / 500 mA
3.3 V and 5 V Input Logic Compatible
Up to VCC Swing on Input Pins
Extended Allowable Negative Bridge Pin Voltage Swing to 10 V
for Signal Propagation
Matched Propagation Delays Between Both Channels
Outputs in Phase with the Inputs
Independent Logic Inputs to Accommodate All Topologies (Version A)
Cross Conduction Protection with 100 ns Internal Fixed Dead Time
(Version B)
Under VCC LockOut (UVLO) for Both Channels
PintoPin Compatible with Industry Standards
These are PbFree Devices
Typical Applications
HalfBridge Power Converters
Any Complementary Drive Converters (Asymmetrical HalfBridge,
Active Clamp) (A Version Only).
FullBridge Converters
http://onsemi.com
MARKING
DIAGRAMS
8
SOIC8
5109x
D SUFFIX
ALYW
1 CASE 751
G
1
5109 = Specific Device Code
x = A or B version
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = PbFree Package
PINOUT INFORMATION
VCC
IN_HI
IN_LO
GND
18
27
36
45
VBOOT
DRV_HI
BRIDGE
DRV_LO
SOIC8
ORDERING INFORMATION
Device
NCP5109ADR2G
Package
Shipping
SOIC8 2500 / Tape & Reel
(PbFree)
NCP5109BDR2G SOIC8 2500 / Tape & Reel
(PbFree)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2013
December, 2013 Rev. 0
1
Publication Order Number:
NCP5109/D

1 page




NCP5109B pdf
NCP5109A, NCP5109B
ELECTRICAL CHARACTERISTIC (VCC = Vboot = 15 V, VGND = Vbridge, 40°C < TJ < 125°C, Outputs loaded with 1 nF)
TJ 40°C to 125°C
Rating
Symbol Min Typ Max
OUTPUT SECTION
Units
Output high short circuit pulsed current VDRV = 0 V, PW v 10 ms (Note 1)
Output low short circuit pulsed current VDRV = VCC, PW v 10 ms (Note 1)
Output resistor (Typical value @ 25°C) Source
Output resistor (Typical value @ 25°C) Sink
High level output voltage, VBIASVDRV_XX @ IDRV_XX = 20 mA
Low level output voltage VDRV_XX @ IDRV_XX = 20 mA
DYNAMIC OUTPUT SECTION
IDRVsource
IDRVsink
ROH
ROL
VDRV_H
VDRV_L
250 mA
500 mA
30 60 W
10 20 W
0.7 1.6
V
0.2 0.6
V
Turnon propagation delay (Vbridge = 0 V)
tON
100 170
ns
Turnoff propagation delay (Vbridge = 0 V or 50 V) (Note 2)
tOFF
100 170
ns
Output voltage rise time (from 10% to 90% @ VCC = 15 V) with 1 nF load tr 85 160 ns
Output voltage fall time (from 90% to 10% @VCC = 15 V) with 1 nF load
tf 35 75 ns
Propagation delay matching between the High side and the Low side
@ 25°C (Note 3)
Dt 20 35 ns
Internal fixed dead time (only valid for B version) (Note 4)
DT 65 100 190 ns
Minimum input width that changes the output
Maximum input width that does not change the output
INPUT SECTION
tPW1
tPW2
− − 50 ns
20
ns
Low level input voltage threshold
Input pulldown resistor (VIN < 0.5 V)
High level input voltage threshold
Logic “1” input bias current @ VIN_XX = 5 V @ 25°C
Logic “0” input bias current @ VIN_XX = 0 V @ 25°C
SUPPLY SECTION
VIN − − 0.8 V
RIN 200 kW
VIN 2.3 − − V
IIN+ 5 25 mA
IIN− − 2.0 mA
VCC UV Startup voltage threshold
VCC UV Shutdown voltage threshold
Hysteresis on VCC
Vboot Startup voltage threshold reference to bridge pin
(Vboot_stup = Vboot Vbridge)
VCC_stup
8.0
8.9
9.9
VCC_shtdwn
7.3
8.2
9.1
VCC_hyst
0.3
0.7
Vboot_stup
8.0
8.9
9.9
V
V
V
V
Vboot UV Shutdown voltage threshold
Vboot_shtdwn 7.3 8.2 9.1
V
Hysteresis on Vboot
Vboot_shtdwn 0.3
0.7
V
Leakage current on high voltage pins to GND
(VBOOT = VBRIDGE = DRV_HI = 200 V)
Consumption in active mode (VCC = Vboot, fsw = 100 kHz and 1 nF load on
both driver outputs)
IHV_LEAK
ICC1
5 40 mA
4 5 mA
Consumption in inhibition mode (VCC = Vboot)
ICC2
250 400
mA
VCC current consumption in inhibition mode
ICC3
200 mA
Vboot current consumption in inhibition mode
ICC4
50 mA
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
1. Parameter guaranteed by design.
2. Turnoff propagation delay @ Vbridge = 200 V is guaranteed by design.
3. See characterization curve for Dt parameters variation on the full range temperature.
4. Version B integrates a dead time in order to prevent any cross conduction between DRV_HI and DRV_LO. See timing diagram of Figure 10.
5. Timing diagram definition see: Figure 7, Figure 8 and Figure 9.
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5

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NCP5109B arduino
NCP5109A, NCP5109B
CHARACTERIZATION CURVES
1.4
1.2
1
0.8
0.6
0.4
0.2
0
10 12 14 16 18 20
VCC, VOLTAGE (V)
Figure 23. Low Level Input Voltage Threshold
vs. Supply Voltage (VCC = VBOOT)
2.5
2
1.5
1
0.5
0
10 12 14 16 18 20
VCC, VOLTAGE (V)
Figure 25. High Level Input Voltage Threshold
vs. Supply Voltage (VCC = VBOOT)
4
3.5
3
2.5
2
1.5
1
0.5
0
10 12 14 16 18 20
VCC, VOLTAGE (V)
Figure 27. Logic “0” Input Current vs. Supply
Voltage (VCC = VBOOT)
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
40 20
0 20 40 60 80
TEMPERATURE (°C)
100 120
Figure 24. Low Level Input Voltage Threshold
vs. Temperature
2.5
2.0
1.5
1.0
0.5
0.0
40 20
0 20 40 60 80
TEMPERATURE (°C)
100 120
Figure 26. High Level Input Voltage Threshold
vs. Temperature
6
5.5
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
40
20 0
20 40 60 80 100
TEMPERATURE (°C)
Figure 28. Logic “0” Input Current vs.
Temperature
120
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