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PDF MCIMX50 Data sheet ( Hoja de datos )
| Número de pieza | MCIMX50 | |
| Descripción | i.MX50 Applications Processors | |
| Fabricantes | Freescale Semiconductor | |
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Freescale Semiconductor
Data Sheet: Technical Data
Document Number: IMX50CEC
Rev. 7, 10/2013
MCIMX50
i.MX50 Applications
Processors for
Consumer Products
Package Information
Plastic Package
Case 416 MAPBGA 13 x 13 mm, 0.5 mm pitch
Case 416 PoPBGA 13 x 13 mm, 0.5 mm pitch
Case 400 MAPBGA 17 x 17 mm, 0.8 mm pitch
Ordering Information
See Table 1 on page 7 for ordering information.
1 Introduction
The i.MX50 applications processors are
multimedia-focused products offering high-performance
processing optimized for lowest power consumption.
The i.MX50 processors are Freescale Energy Efficiency
Solutions products.
The i.MX50 is optimized for portable multimedia
applications and features Freescale’s advanced
implementation of the ARM Cortex-A8® core, which
operates at speeds as high as 1 GHz. The i.MX50
provides a powerful display architecture, including a 2D
Graphics Processing Unit (GPU) and Pixel Processing
Pipeline (ePXP). Additionally, the i.MX50 includes a
complete integration of the electrophoretic display
function. The i.MX50 supports DDR2, LPDDR2, and
LPDDR1 DRAM at clock rate up to 266 MHz to enable
a range of performance and power trade-offs.
The flexibility of the i.MX50 architecture allows it to be
used in a variety of applications. As the heart of the
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1. Product Overview . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 7
1.4. Part Number Feature Comparison . . . . . . . . . . . . . 8
1.5. Package Feature Comparison . . . . . . . . . . . . . . . . 9
2. Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3. Modules List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1. Special Signal Considerations . . . . . . . . . . . . . . . 17
4. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 20
4.1. Chip-Level Conditions . . . . . . . . . . . . . . . . . . . . . 21
4.2. Supply Power-Up/Power-Down Requirements and
Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.3. I/O DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 31
4.4. Output Buffer Impedance Characteristics . . . . . . 37
4.5. I/O AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 41
4.6. System Modules Timing . . . . . . . . . . . . . . . . . . . . 48
4.7. External Interface Module (EIM) . . . . . . . . . . . . . . 60
4.8. DRAM Timing Parameters . . . . . . . . . . . . . . . . . . 68
4.9. External Peripheral Interfaces . . . . . . . . . . . . . . . 73
5. Package Information and Contact Assignments . . . . . 101
5.1. 13 x 13 mm, 0.5 mm Pitch, 416 Pin MAPBGA Package
Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
5.2. 13 x 13 mm, 0.5 mm Pitch, 416 Pin PoPBGA Package
Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
5.3. 17 x 17 mm, 0.8 mm Pitch, 400 Pin MAPBGA Package
Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
5.4. Signal Assignments . . . . . . . . . . . . . . . . . . . . . . 124
6. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Freescale reserves the right to change the detail specifications as may be required
to permit improvements in the design of its products.
© 2011–2013 Freescale Semiconductor, Inc. All rights reserved.
1 page  
Introduction
– GPU 2D
– SDMA
– USBOH1 (USB OTG and host controller complex)
– FEC Ethernet controller
• MAX AHB crossbar (133 MHz)—This connects the various AHB bus sub-segments in the system
and provides decode into the following slaves:
— IP-Bus 1 (66 MHz)—This bus segment contains peripherals accessible by the ARM core and
without DMA capability
— IP-Bus 2 (66 MHz)—This bus segment contains peripherals accessible by the ARM core and
without DMA capability
— APBH DMA bridge (133 MHz)—The APBH DMA bridge is a master to the MAX for its
memory-side DMA operations. The APBH bus is an AMBA APB slave bus providing
peripheral access to many of the high-speed IP blocks on the i.MX50.
• IP-Bus 3 (66 MHz)—This third peripheral bus segment contains peripherals accessible by the
ARM core and SDMA and as such houses peripherals with DMA capability. The IP-Bus 3 can be
accessed by the ARM CPU through IP-Bus 1 and SPBA.
• Quality of service controller (QoSC)—This provides both soft and dynamic arbitration/priority
control. The QoSC works in conjunction with the critical display modules such as the eLCDIF and
EPDC to provide dynamic priority control, based on real-time metrics.
The i.MX50 makes use of dedicated hardware accelerators to achieve state-of-the-art multimedia
performance. The use of hardware accelerators provides both high performance and low power
consumption, while freeing up the CPU core for other tasks.
The i.MX50 incorporates the following hardware accelerators:
• GPU2Dv1—2D Graphics accelerator, OpenVG 1.1, 200 Mpix/s performance
• ePXP—enhanced PiXel Processing Pipeline off loading key pixel processing operations required
to support both LCD and EPD display applications
The i.MX50 includes the following interfaces to external devices:
NOTE
Not all the interfaces are available simultaneously depending on I/O
multiplexer configuration.
• Displays:
— EPDC (i.MX508 Only)—Supporting direct-driver TFT backplanes beyond 2048 × 1536 at
106 Hz refresh (or 4096 × 4096 at 20 Hz)
— eLCDIF—Supporting beyond SXGA + (1400 × 1050) at 60 Hz resolutions with up to a 32-bit
display interface
— On the i.MX508, both displays can be active simultaneously. If both displays are active, the
eLCDIF only provides a 16-bit interface due to pin muxing.
• Expansion cards:
— Four SD/MMC card
Freescale Semiconductor
i.MX50 Applications Processors for Consumer Products, Rev. 7
5
5 Page 
NOTE
The numbers in brackets indicate the number of module instances. For
example, PWM (2) indicates two separate PWM peripherals.
Modules List
3 Modules List
The i.MX50 processor contains a variety of digital and analog modules that are described in Table 4 in
alphabetical order.
Table 4. i.MX50 Digital and Analog Modules
Block
Mnemonic
Block Name Subsystem
Brief Description
ARM
Cortex-A8
EPDC
ePXP
eLCDIF
AUDMUX
CAMP-1
ARM Cortex-A8 ARM
Platform
The ARM Cortex-A8 Core Platform consists of the ARM Cortex-A8 processor
and its essential sub-blocks. It contains the 32 Kbyte L1 instruction cache,
32 Kbyte L1 data cache, Level 2 cache controller and a 256 Kbyte L2 cache.
The platform also contains an event monitor and debug modules. It also has
a NEON coprocessor with SIMD media processing architecture, register file
with 32 × 64-bit general-purpose registers, an Integer execute pipeline (ALU,
Shift, MAC), dual, single-precision floating point execute pipeline (FADD,
FMUL), load/store and permute pipeline, and a non-pipelined vector floating
point (VFP Lite) coprocessor supporting VFPv3.
Electrophoretic Display
Display
Peripherals
Controller
The EPDC is a feature-rich, low power, and high-performance direct-drive
active matrix EPD controller. It is specifically designed to drive E-INKTM EPD
panels supporting a wide variety of TFT backplanes.
enhanced PiXel Display
Processing
Peripherals
Pipeline
A high-performance pixel processor capable of 1 pixel/clock performance for
combined operations such as color-space conversion, alpha blending,
gamma-mapping, and rotation. The ePXP is enhanced with features
specifically for grayscale applications. In addition, the ePXP supports
traditional pixel/frame processing paths for still-image and video processing
applications allowing it to interface with the integrated LCD controller
(eLCDIF).
enhanced LCD Display
Interface
Peripherals
The eLCDIF is a high-performance LCD controller interface supporting a rich
set of modes allowing inter operability with a wide variety of LCD panels,
including DOTCK/RGB and smart panels. The module also supports a
synchronous operation with the ePXP to allow the processed frames to be
passed from the ePXP to the eLCDIF through an on-chip SRAM buffer. The
eLCDIF can support up to 32-bit interfaces.
Digital Audio
Mux
Slave
Connectivity
Peripherals
The AUDMUX is a programmable interconnect for voice, audio, and
synchronous data routing between host serial interfaces (for example, SSI1
and SSI2) and peripheral serial interfaces (audio and voice codecs). The
AUDMUX has six ports (two internal and four external) with identical
functionality and programming models. A desired connectivity is achieved by
configuring two or more AUDMUX ports.
Clock Amplifier Clocks,
Clock Amplifier
Resets, and
Power Control
Freescale Semiconductor
i.MX50 Applications Processors for Consumer Products, Rev. 7
11
11 Page | ||
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| PDF Descargar | [ Datasheet MCIMX50.PDF ] | |
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