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PDF LC89091JA Data sheet ( Hoja de datos )
| Número de pieza | LC89091JA | |
| Descripción | Digital Audio Interface Receiver | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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Ordering number : ENA2172A
LC89091JA
CMOS LSI
Digital Audio Interface Receiver
http://onsemi.com
1. Overview
The LC89091JA is a digital audio interface receiver that demodulates signals according to the data transfer format
between digital audio devices via IEC60958, IEC61937 and JEITA CPR-1205.
It supports demodulation sampling frequencies of up to 192kHz.
The LC89091JA adjusts to using in various systems including AV receivers, digital TVs and DVD recorders.
2. Features
S/PDIF demodulation process according to IEC60958, IEC61937 and JEITA CPR-1205
Outputs master clock: 512fs, 256fs and 128fs (with output frequency automatic adjustment function)
Audio data output interface: 24-bit I2S and MSB first left justified
I2C microcontroller interface (with address automatic increment function)
Built-in power-on reset circuit
Supply voltages: 3.0 to 3.6V
Package: SSOP16 (lead-free and halogen-free)
Operation guarantee temperature: 30 to 70°C
Applicaitons
Consumer Audio
Digital Audio Interface
End Products
AV Receiver
Home Theater-in-a-Box
Mini Compo
Sound Bar
Headphone Amplifier
SSOP16(225mil)
* I2C Bus is a trademark of Philips Corporation.
ORDERING INFORMATION
See detailed ordering and shipping information on page 30 of this data sheet.
Semiconductor Components Industries, LLC, 2014
March, 2014
31214HK 20140227-S00001/201813HK No.A2172-1/30
1 page  
LC89091JA
7. Electrical Characteristics
7.1 Absolute Maximum Ratings
Table 7.1: Absolute Maximum Ratings at GND=0V
Parameter
Symbol
Conditions
Ratings
Maximum supply voltage
Input voltage
Output voltage
Storage ambient temperature
VDD max
VIN
VOUT
Tstg
7.1.1
7.1.2
7.1.3
-0.3 to 4.6
-0.3 to VDD max+0.3 (max.4.6Vp-p)
-0.3 to VDD max+0.3 (max.4.6Vp-p)
-55 to 125
Operating ambient temperature
Topr
-30 to 70
Maximum input/output current
IIN, IOUT
7.1.4
20
7.1.1: VDD pin
7.1.2: SCL, SDA, RXIN, MPIO, XIN and SDIN pins
7.1.3: SDA, ERR, GPO, MPIO, MCKO, BCKO, LRCKO, DATAO and XOUT pins
7.1.4: Per input/output pin
Unit
V
V
V
C
C
mA
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed,
damage may occur and reliability may be affected.
7.2 Allowable Operating Range
Parameter
Table 7.2: Recommended Operating Conditions at GND=0V
Symbol
Conditions
min
typ
Supply voltage
Input voltage range
Output load capacitance
Output load capacitance
Operating temperature
VDD
VIN
CL1
CL2
Vopr
7.2.1
7.2.2
7.2.3
7.2.4
3.0 3.3
0
-30 25
7.2.1: VDD pin
7.2.2: SCL, SDA, RXIN, MPIO, XIN and SDIN pins
7.2.3: MCKO pin
7.2.4: Output pins expect MCKO pin
max
3.6
3.6
20
30
70
Unit
V
V
pF
pF
C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended
Operating Ranges limits may affect device reliability.
7.3 DC Characteristics
Table 7.3: DC Characteristics at Ta=-30 to 70C, VDD=3.0 to 3.6V, GND=0V
Parameter
Symbol
Conditions
min
max
Input, High
VIH 7-3-1
0.7 VDD
Input, Low
VIL
Input, High
VIH 7.3.2
2.0
Input, Low
VIL
Output, High
VOH
7.3.3
VDD-0.8
Output, Low
VOL
VDD Supply Current
IDD1
7.3.4
VDD Supply Current
IDD2
7.3.5
7.3.1: CMOS-compatible: XIN pin (while external clock inputs)
7.3.2: TTL-compatible: SCL, SDA, RXIN, MPIO and SDIN pins
7.3.3: IOH=-4mA, IOL=4mA: ERR, MCKO, BCKO, LRCKO, DATAO and XOUT output pins
IOH=-2mA, IOL=2mA: SDA and MPIO output pins
7.3.4: Input fs: 96kHz, MCKO: 512fs output status
7.3.5: "PDMODE=1"
0.2VDD
0.8
0.4
20
2
Unit
V
V
V
V
V
V
mA
A
No.A2172-5/30
5 Page 
LC89091JA
The PLL clock output frequencies are shown below.
When "PLLACC=1" and "PRSEL[1:0]=01" (512fs) are set, 128kHz, 176.4kHz and 192kHz S/PDIF reception results
in a PLL output frequency that exceeds 50MHz, so direct output to MCKO is not guaranteed.
Table 8.2: PLL Clock Output Frequencies (Bold settings are initial values.)
PLL clock output frequencies (MHz)
S/PDIF
fs
(kHz)
"PLLACC=0"
(Fixed multiple outputs for each input fs band)
"PLLDIV=00"
"PLLDIV=01"
"PLLDIV=10"
"PLLDIV=11"
"PLLACC=1"
(Fixed multiple outputs of input fs)
"PRSEL=00"
"PRSEL=01"
"PRSEL=10"
(256fs)
(512fs)
(128fs)
32 16.38
8.19
16.38
8.19
8.19
16.38
4.09
44.1
22.57
11.28
22.57
11.28
11.28
22.57
5.64
48 24.57
12.28
24.57
12.28
12.28
24.57
6.14
64 16.38
16.38
32.76
32.76
16.38
32.76
8.19
88.2
22.57
22.57
45.15
45.15
22.57
45.15
11.28
96 24.57
24.57
49.15
49.15
24.57
49.15
12.28
128 16.38
16.38
16.38
16.38
32.76
65.54 *
16.38
176.4
22.57
22.57
22.57
22.57
45.15
90.32 *
22.57
192 24.57
24.57
24.57
24.57
49.15
98.30 *
24.57
*: Direct output to the MCKO pin is not guaranteed.
8.5.3 XIN Source Master Clock (XIN, XOUT)
Supply XIN with clocks all the time to be used in the following applications.
1) Clock source when the PLL is unlocked
2) PLL lock-in support
3) Calculation of the S/PDIF input data sampling frequency
24.576MHz clock always has to supply to XIN.
Normally, the oscillation amplifier automatically stops while the PLL is locked, but operation that always operates
regardless of the PLL status can also be set. This is set with the AMPOPR register.
The AMPOPR register must be set before S/PDIF input, or the setting must be completed while the PLL is unlocked.
For fixing a system clock to a XIN clock, PLL is changed into an unlocking state. The ADMODE register always sets
PLL as an unlocking state.
The output clock frequency at the time of XIN source is set up with the XOUTCK register.
Output Pin Name
Master clock
MCKO
Bit clock
BCKO
L/R clock
LRCKO
Table 8.3: List of Output Clock Frequencies
When PLL is unlocked,
XIN source clock (XIN input clock)
When PLL is locked,
PLL source clock (Internal VCO clock)
24.576 MHz
24.576 MHz
512fs
512fs
256fs
128fs
6.144 MHz
3.072 MHz
64fs
96 kHz
48 kHz
fs
No.A2172-11/30
11 Page | ||
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