PDF CY8C24533 Data sheet ( Hoja de datos )

Número de pieza	CY8C24533
Descripción	PSoC Programmable System-on-Chip
Fabricantes	Cypress Semiconductor
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CY8C24533 PSoC® Programmable System-on-Chip™ Features ■ Powerful Harvard Architecture Processor ❐ M8C Processor Speeds to 24 MHz ❐ 8x8 Multiply, 32-Bit Accumulate ❐ Low Power at High Speed ❐ 3.0 to 5.25V Operating Voltage ❐ Industrial Temperature Range: -40°C to +85°C ■ Advanced Peripherals (PSoC Blocks) ❐ 4 Rail-to-Rail Analog PSoC Blocks Provide: • Up to 14-Bit ADCs • Up to 8-Bit DACs • Programmable Gain Amplifiers • Programmable Filters and Comparators ❐ 4 Digital PSoC Blocks Provide: • 8 to 32-Bit Timers, Counters, and PWMs • CRC and PRS Modules • Full-Duplex UART • Multiple SPI™ Masters or Slaves • Connectable to all GPIO pins ❐ Complex Peripherals by Combining Blocks ❐ High-Speed 8-Bit SAR ADC Optimized for Motor Control ■ Precision, Programmable Clocking ❐ Internal ±5% 24/48 MHz Oscillator ❐ High Accuracy 24 MHz with Optional 32 kHz Crystal and PLL ❐ Optional External Oscillator, up to 24 MHz ❐ Internal Oscillator for Watchdog and Sleep ■ Flexible On-Chip Memory ❐ 8K Bytes Flash Program Storage 50,000 Erase/Write Cycles ❐ 256 Bytes SRAM Data Storage ❐ In-System Serial Programming (ISSP) ❐ Partial Flash Updates ❐ Flexible Protection Modes ❐ EEPROM Emulation in Flash ■ Programmable Pin Configurations ❐ 25 mA Sink on All GPIO ❐ Pull Up, Pull Down, High Z, Strong, or Open Drain Drive Modes on All GPIO ❐ Up to Ten Analog Inputs on GPIO ❐ Two 30 mA Analog Outputs on GPIO ❐ Configurable Interrupt on All GPIO ■ Additional System Resources ❐ I2C™ Slave, Master, and Multi-master to 400 kHz ❐ Watchdog and Sleep Timers ❐ User-Configurable Low Voltage Detection ❐ Integrated Supervisory Circuit ❐ On-chip Precision Voltage Reference ■ Complete Development Tools ❐ Free Development Software (PSoC Designer™) ❐ Full-Featured In-Circuit Emulator and Programmer ❐ Full Speed Emulation ❐ Complex Breakpoint Structure ❐ 128K Bytes Trace Memory Logic Block Diagram PSoC CORE Port 3 Port 2 Port 1 Port 0 Analog Drivers System Bus Global Digital Interconnect Global Analog Interconnect SRAM 256 Bytes Interrupt Controller SROM Flash 8K CPUCore (M 8C) Sleep and Watchdog Multiple ClockSources (Includes IMO, ILO, PLL, and ECO) DIGITAL SYSTEM Digital Block Array 1 Row 4 Blocks ANALOG SYSTEM Analog Block Array 2 Columns 4 Blocks SAR8 ADC Analog Ref Analog Input Muxing Digital Clocks Multiply Accum . Decim ator I2C POR and LVD System Resets SYSTEM RESOURCES Internal Voltage Ref. Cypress Semiconductor Corporation • 198 Champion Court Document Number: 001-14643 Rev. D • San Jose, CA 95134-1709 • 408-943-2600 Revised December 05, 2008 [+] Feedback 1 page CY8C24533 Development Tools PSoC Designer is a Microsoft® Windows-based, integrated development environment for the Programmable System-on-Chip (PSoC) devices. The PSoC Designer IDE and application runs on Windows NT 4.0, Windows 2000, Windows Millennium (Me), or Windows XP (Refer Figure 3). PSoC Designer helps the customer to select an operating configuration for the PSoC, write application code that uses the PSoC, and debug the application. This system provides design database management by project, an integrated debugger with In-Circuit Emulator, in-system programming support, and the CYASM macro assembler for the CPUs. PSoC Designer also supports a high level C language compiler developed specifically for the devices in the family. Figure 3. PSoC Designer Subsystems PSoC Designer Graphical Designer Interface Context Sensitive Help Importable Design Database Device Database Application Database Project Database User Modules Library PSoC Designer Core Engine PSoC Configuration Sheet Manufacturing Information File Emulation Pod In-Circuit Emulator Device Programmer PSoC Designer Software Subsystems Device Editor The Device Editor subsystem allows the user to select different onboard analog and digital components called user modules using the PSoC blocks. Examples of user modules are ADCs, DACs, Amplifiers, and Filters. The device editor also supports easy development of multiple configurations and dynamic reconfiguration. Dynamic configu- ration allows for changing configurations at run time. PSoC Designer sets up power on initialization tables for selected PSoC block configurations and creates source code for an application framework. The framework contains software to operate the selected components and, if the project uses more than one operating configuration, contains routines to switch between different sets of PSoC block configurations at run time. PSoC Designer can print out a configuration sheet for a given project configuration for use during application pro- gramming in conjunction with the Device Data Sheet. Once the framework is generated, the user can add application-specific code to flesh out the framework. It’s also possible to change the selected components and regenerate the framework. Design Browser The Design Browser allows users to select and import precon- figured designs into the user’s project. Users can easily browse a catalog of preconfigured designs to facilitate time-to-design. Examples provided in the tools include a 300-baud modem, LIN Bus master and slave, fan controller, and magnetic card reader. Application Editor In the Application Editor you can edit your C language and Assembly language source code. You can also assemble, com- pile, link, and build. Assembler. The macro assembler allows the assembly code to be merged seamlessly with C code. The link libraries auto- matically use absolute addressing or can be compiled in relative mode, and linked with other software modules to get absolute addressing. C Language Compiler. A C language compiler is available that supports the PSoC family of devices. Even if you have never worked in the C language before, the product quickly allows you to create complete C programs for the PSoC family devices. The embedded, optimizing C compiler provides all the features of C tailored to the PSoC architecture. It comes complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. Document Number: 001-14643 Rev. D Page 5 of 34 [+] Feedback 5 Page Table 4. Register Map Bank 0 Table: User Space (continued) CY8C24533 Gray fields are reserved. 3E 3F # Access is bit specific. 7E 7F Table 5. Register Map Bank 1 Table: Configuration Space BE CPU_SCR1 FE # BF CPU_SCR0 FF # PRT0DM0 PRT0DM1 PRT0IC0 PRT0IC1 PRT1DM0 PRT1DM1 PRT1IC0 PRT1IC1 PRT2DM0 PRT2DM1 PRT2IC0 PRT2IC1 PRT3DM0 PRT3DM1 PRT3IC0 PRT3IC1 DBB00FN DBB00IN DBB00OU DBB01FN DBB01IN DBB01OU DCB02FN DCB02IN DCB02OU DCB03FN DCB03IN DCB03OU Gray fields are reserved. 00 RW 01 RW 02 RW 03 RW 04 RW 05 RW 06 RW 07 RW 08 RW 09 RW 0A RW 0B RW 0C RW 0D RW 0E RW 0F RW 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 RW CLK_CR0 21 RW CLK_CR1 22 RW ABF_CR0 23 AMD_CR0 24 RW 25 RW 26 RW AMD_CR1 27 ALT_CR0 28 RW 29 RW 2A RW 2B 2C RW TMP_DR0 2D RW TMP_DR1 2E RW TMP_DR2 2F TMP_DR3 30 ACB00CR3 31 ACB00CR0 32 ACB00CR1 33 ACB00CR2 34 ACB01CR3 35 ACB01CR0 36 ACB01CR1 # Access is bit specific. Document Number: 001-14643 Rev. *D 40 80 41 81 42 82 43 83 44 ASD11CR0 84 RW 45 ASD11CR1 85 RW 46 ASD11CR2 86 RW 47 ASD11CR3 87 RW 48 88 49 89 4A 8A 4B 8B 4C 8C 4D 8D 4E 8E 4F 8F 50 90 GDI_O_IN 51 91 GDI_E_IN 52 92 GDI_O_OU 53 93 GDI_E_OU 54 ASC21CR0 94 RW 55 ASC21CR1 95 RW 56 ASC21CR2 96 RW 57 ASC21CR3 97 RW 58 98 59 99 5A 9A 5B 9B 5C 9C 5D 9D OSC_GO_EN 5E 9E OSC_CR4 5F 9F OSC_CR3 60 RW A0 OSC_CR0 61 RW A1 OSC_CR1 62 RW A2 OSC_CR2 63 RW A3 VLT_CR 64 A4 VLT_CMP 65 A5 66 RW A6 67 RW A7 68 SARADC_TRS A8 RW IMO_TR 69 SARADC_TRCL A9 RW ILO_TR 6A SARADC_TRCH AA RW BDG_TR 6B SARADC_CR2 AB # ECO_TR 6C RW SARADC_LCR AC RW 6D RW AD 6E RW AE 6F RW AF 70 RW RDI0RI B0 RW 71 RW RDI0SYN B1 RW 72 RW RDI0IS B2 RW 73 RW RDI0LT0 B3 RW 74 RW RDI0LT1 B4 RW 75 RW RDI0RO0 B5 RW 76 RW RDI0RO1 B6 RW C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 RW D1 RW D2 RW D3 RW D4 D5 D6 D7 D8 D9 DA DB DC DD RW DE RW DF RW E0 RW E1 RW E2 RW E3 RW E4 R E5 E6 E7 E8 W E9 W EA RW EB W EC ED EE EF F0 F1 F2 F3 F4 F5 F6 Page 11 of 34 [+] Feedback 11 Page

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