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PDF LE2464C Data sheet ( Hoja de datos )
| Número de pieza | LE2464C | |
| Descripción | 64-kb I2C CMOS Serial EEPROM | |
| Fabricantes | ON Semiconductor | |
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LE2464C
64 kb I2C CMOS Serial EEPROM
Overview
The LE2464C is two-wire serial interface EEPROM (Electrically
Erasable and Programmable ROM). This device realizes high speed
and a high level reliability by high performance CMOS EEPROM
technology. This device is compatible with I2C memory protocol,
therefore it is best suited for application that requires re-writable
nonvolatile parameter memory.
www.onsemi.com
Function
Capacity
: 64k bits (8k 8 bits)
Single supply voltage
Operating temperature
Interface
: 1.7 V to 3.6 V
: 40ºC to +85ºC
: Two wire serial interface (I2C Bus*)
WLCSP6, 0.80x1.20
Operating clock frequency : 400 kHz
Low Power consumption
: Standby
: 2 µA (max.)
: Active (Read) : 0.5 mA (max.)
Automatic page write mode : 32 Bytes
Read mode
: Sequential Read and random read
Slave Address : Slave address in 7 bit format is 050 or 054 depending of polarity of pin B3 (TEST)
Erase/Write cycles : 106 cycles (Page Write)
Data Retention : 20 years
High reliability : Adopts proprietary symmetric memory array configuration (USP6947325)
Hardware write protect feature
Noise filters connected to SCL and SDA pins
Incorporates a feature to prohibit write operations under low voltage conditions.
Package
: WLP6(1.200.80) 0.33mm height
Specifications
Absolute Maximum Ratings at Ta = 25C
Parameter
Supply voltage
DC input voltage
Over-shoot voltage
Storage temperature
Symbol
Tstg
Conditions
Ratings
0.5 to +4.6
0.5 to VCC+0.5
1.0 to VCC+1.0
65 to +150
Unit
V
V
V
C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed,
damage may occur and reliability may be affected.
* This product is licensed from Silicon Storage Technology, Inc. (USA).
ORDERING INFORMATION
See detailed ordering and shipping information on page 16 of this data sheet.
© Semiconductor Components Industries, LLC, 2016
August 2016 - Rev. 3
1
Publication Order Number :
LE2464C/D
1 page  
Pin Assignment
Top View
A SCL WP VCC
B SDA GND TEST
1 23
LE2464C
Ball side View
SDA
GND
TEST
B
SCL WP VCC A
1 23
Pin Descriptions
A1 SCL
A2 WP
A3 VCC
B1 SDA
B2 GND
B3 TEST
Serial clock input
Write protect
Power supply
Serial data in/output
Ground
Slave Device Address 2
Block Diagram
TEST
WP
SCL
SDA
Write controller
High voltage generator
EEPROM Array
Y decoder & Sense AMP
Serial-Parallel converter
www.onsemi.com
5
5 Page 
LE2464C
7) EEPROM Read Operation
7)-1. Current Address Read
The device has an internal address counter. It maintains that last address during the last read or write
operation, with incremented by one. The current address read accesses the address kept by the internal
address counter. After receiving a start condition and the device address word with the 8th bit = 1 (Read),
the EEPROM outputs the 8-bit current address data from following acknowledgement 0. If the EEPROM
receives acknowledgement 1 and a following stop condition, the EEPROM stops the read operation and
is returned to a standby mode. In case the EEPROM has accessed the last address of the last page at
previous read operation, the current address will roll over and returns to zero address. In case EEPROM
has accessed the last address of the last page at previous write operation, the current address roll over
within page addressing and returns to the first address in the same page.
The current address is valid while power is on. After power on, the current address will be reset (all 0).
Note: After the page write operation, the current address is the specified memory address in the last page
write, if the write data is more than 32-bytes.
SDA
Device Address
Data (n+1)
1 0 1 0 S2 S1 S0 R D7 D6 D5 D4 D3 D2 D1 D0
ACK
R/W
NO ACK
Access from master device
7)-2. Random Read
The random read requires a dummy write to set read address. The EEPROM receives a start condition
and the device address word with the 8th bit = 0 (write), the memory address. The EEPROM outputs
acknowledgement 0 after receiving memory address then enters a current address read with receiving a
start condition. The EEPROM outputs the read data of the address which was defined in the dummy write
operation. After receiving no acknowledgement and a following stop condition, the EEPROM stops the
random read operation and returns to a standby mode.
SDA
Device Address
Word Address(n)
1 0 1 0 S2 S1S0 W
A
15
A
14
A
13
A
12
A
11
A
10
A9
A8
ACK
R/W
Dummy Write
A7 A6 A5 A4 A3 A2 A1 A0
ACK
ACK
Device Address
Data(n)
1 0 1 0 S2 S1 S0 R D7D6 ~ D1D0
ACK
ACK
NO ACK
R/W
Current Read
A15 ~ A13: Don’t Care
Access from master device
www.onsemi.com
11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet LE2464C.PDF ] | |
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