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PDF LE25CB643TT-BH Data sheet ( Hoja de datos )
| Número de pieza | LE25CB643TT-BH | |
| Descripción | 64 kb SPI CMOS Serial EEPROM | |
| Fabricantes | ON Semiconductor | |
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Ordering number : ENA2255
LE25CB643TT-BH
CMOS IC
64 kb SPI CMOS Serial EEPROM
http://onsemi.com
Overview
The LE25CB643TT-BH (hereinafter referred to as ‘this device’) is serial peripheral interface EEPROM (Electrically
Erasable and Programmable ROM). This device realizes high speed and a high level reliability by incorporating high
performance CMOS EEPROM technology. This device is compatible with SPI memory protocol, therefore it is best
suited for application that requires re-writable nonvolatile parameter memory. And this device has 32bytes page write
function for high speed data re-write.
Function
• Capacity
: 64k bits (8k × 8 bits)
• Single supply voltage
: 2.7V to 5.5V
• Operating temperature
: -40ºC to +85ºC
• Interface
: SPI Mode0 and Mode3
correspondence
• Operating clock frequency : 5MHz
• Low Power consumption
: Standby
: Read
: 3µA (max.)
: 1mA (max.)
Micro8
: Write
: 3mA (max.)
• Automatic page write mode : 32 Bytes
• Write cycle time
• Erase/Write cycles
: 5ms
: 106 cycles
• Data Retention
: 20 years
• High reliability
: Adopts proprietary symmetric memory array configuration (USP6947325)
Incorporates a feature to prohibit write operations under low voltage conditions.
• Package
: LE25CB643TT-BH Micro8
* This product is licensed from Silicon Storage Technology, Inc. (USA).
ORDERING INFORMATION
See detailed ordering and shipping information on page 17 of this data sheet.
Semiconductor Components Industries, LLC, 2013
December, 2013
D1813HKPC 20131129-S00001 No.A2255-1/17
1 page  
Pin Assignment
LE25CB643TT-BH
CS
SO
WP
VSS
1
2
3
4
8 VDD
7 HOLD
6 SCK
5 SI
Pin Descriptions
PIN1
CS
PIN2
SO
PIN3
WP
PIN4
PIN5
VSS
SI
PIN6
SCK
PIN7
HOLD
PIN8
VDD
Chip select
Serial data output
Write-protect
Ground
Serial data input
Serial clock
Hold
Power supply
Block Diagram
ADDRESS
BUFFERS
&
LATCHES
X-
DECODER
EEPROM
Cell Array
Y-DECODER
CONTROL
LOGIC
I/O BUFFERS
&
DATA LATCHES
SERIAL INTERFACE
CS SCK SI SO WP HOLD
No.A2255-5/17
5 Page 
LE25CB643TT-BH
2-2. Status Register Write (WRSR)
By Status Register Write, BP0, BP1 and SRWP can be rewritten. RDY, WEN, Bit4, Bit5 and Bit6 are read-only, BP0,
BP1 and SRWP are non-volatile.
A timing waveform is shown in Figure6 and a flow chart is shown in Figure11.
Status Register Write command consists of the 1st bus cycle and the 2nd bus cycle, and internal Write operation starts
with the rising edge of CS after inputting data after OP-code (01h). Internal write operation is automatically performed
inside the device and a Status Register Write rewrites BP0, BP1 and SRWP non-volatilized data. The write-in data to
read-only bits (RDY, WEN, Bit4, Bit5, Bit 6) are don't care.
The end of a Status Register Write is detectable with RDY of a Status Register Read.
The number of times of rewriting of a Status Register Write is 1,000 times (Min).
In order to perform a Status Register Write, it is necessary to change WEN of a Status Register into "1" state for WP
pin.
Figure 6: Status Register Write Timing Diagram
CS
tWPS
Self-timed
Write Cycle
tWC
tWPH
WP
Mode3
SCK
Mode0
SI
0 1 2 3 4 5 6 7 8 15
8CLK
01h
(0000001)
DATA
High Impedance
SO
2-3. Status Register Description
RDY (Bit0)
The end of a Write is detectable with RDY. If device is in a busy state RDY is in "1", and the Write will be ended in "0"
states.
WEN (Bit1)
It is detectable whether a Write is possible with WEN. If WEN is in "0" state, even if it inputs a Write command, Device
will not perform write operation. If WEN is in "1" state, Write is possible to the area by which block protection is not
carried out.
WEN is controllable with a Write Enable command and a Write disable command. WEN will be in "1" state with a
Write Enable command (06h), and will be in "0" states with a Write disable command (04h).
Moreover, in the following state, automatically, WEN will be in "0" states and an unprepared Write will be prevented.
• At the time of a power-up
• After a write is completed
• After a Status Register Write is completed
* WEN keeps previous status, if input command is incomplete, execute write operation for protected address and not
execute internal write.
No.A2255-11/17
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet LE25CB643TT-BH.PDF ] | |
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