DataSheet.es    


PDF ASM5P2304A Data sheet ( Hoja de datos )

Número de pieza ASM5P2304A
Descripción 3.3V Zero Delay Buffer
Fabricantes ON Semiconductor 
Logotipo ON Semiconductor Logotipo



Hay una vista previa y un enlace de descarga de ASM5P2304A (archivo pdf) en la parte inferior de esta página.


Total 8 Páginas

No Preview Available ! ASM5P2304A Hoja de datos, Descripción, Manual

ASM5P2304A
3.3 V Zero Delay Buffer
Description
ASM5P2304A is a versatile, 3.3 V zerodelay buffer designed to
distribute highspeed clocks in PC, workstation, datacom, telecom
and other highperformance applications. It is available in 8pin
package. The part has an onchip PLL which locks to an input clock
presented on the REF. The PLL feedback is required to be driven to
FBK pin, and can be obtained from one of the outputs. The
inputtooutput propagation delay is guaranteed to be less than
±250 pS, and the outputtooutput skew is guaranteed to be less than
200 pS.
ASM5P2304A has two banks of two outputs each. Multiple
ASM5P2304A devices can accept the same input clock and distribute
it. In this case the skew between the outputs of the two devices is
guaranteed to be less than 500 pS.
ASM5P2304A is available in two different configurations. Refer to
ASM5P2304A Configurations Table. The ASM5P2304A1 is the base
part, where the output frequencies equal the reference if there is no
counter in the feedback path. The ASM5P2304A1H is the highdrive
version of the 1 and the rise and fall times on this device are faster.
ASM5P2304A2 allows the user to obtain REF and 1/2x or 2x
frequencies on each output bank. The exact configuration and output
frequencies depend on which output drives the feedback pin.
Features
Zero InputOutput Propagation Delay, Adjustable by Capacitive
Load on FBK Input
Multiple Configurations
Refer to ASM5P2304A Configurations Table
Input Frequency Range: 10 MHz to 133 MHz
Multiple Lowskew Outputs
OutputOutput Skew less than 200 pS
DeviceDevice Skew less than 500 pS
Two Banks of Two Outputs Each
Less than 200 pS CycletoCycle Jitter
(1, 1H, 2, 2H)
8pin SOIC Package
3.3 V Operation
Commercial and Industrial Temperature Range
Advanced 0.35 m CMOS Technology
These Devices are PbFree, Halogen Free/BFR Free and are RoHS
Compliant
http://onsemi.com
SOIC8
S SUFFIX
CASE 751BD
PIN CONFIGURATION
1
REF
FBK
CLKA1
VDD
CLKA2
CLKB2
GND
CLKB1
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
© Semiconductor Components Industries, LLC, 2011
August, 2011 Rev. 3
1
Publication Order Number:
ASM5P2304A/D

1 page




ASM5P2304A pdf
ASM5P2304A
Table 6. SWITCHING CHARACTERISTICS (Notes 5, 6)
Parameter
Test Conditions
Output Frequency
30 pF load
(1, 1H) devices
(2, 2H) devices
15 pF load
(1, 1H) devices
(2, 2H) devices
Duty Cycle (Note 7)
(1, 2, 1H, 2H)
Duty Cycle (Note 7)
(1, 2,1H, 2H)
Output Rise Time (Note 7)
(1, 2)
Measured at 1.4 V,
FOUT < 66.66 MHz, 30 pF load
Measured at 1.4 V,
FOUT 50 MHz, 15 pF load
Measured between 0.8 V
and 2.0 V, 30 pF load
Commercial temp.
Industrial temp.
Output Rise Time (Note 7)
(1H, 2H)
Measured between 0.8 V
and 2.0 V, 30 pF load
Commercial temp.,
Industrial temp.
Output Rise Time (Note 7)
(1, 2)
Measured between 0.8 V
and 2.0 V, 15 pF load
Output Fall Time (Note 7)
(1, 2)
Measured between 2.0 V
and 0.8 V, 30 pF load
Commercial temp.
Industrial temp.
Output Fall Time (Note 7)
(1H, 2H)
Measured between 2.0 V
and 0.8 V, 30 pF load
Commercial temp.,
Industrial temp.
Output Fall Time (Note 7)
(1, 2)
Measured between 2.0 V
and 0.8 V, 15 pF load
Outputtooutput skew on same bank
(1, 1H, 2, 2H) (Note 7)
All outputs equally loaded
Output bank A tooutput bank B
skew (1, 1H)
All outputs equally loaded
Output bank A to output Bank B
skew (2, 2H) (Note 7)
All outputs equally loaded
Delay, REF Rising Edge to FBK
Rising Edge (Note 7)
Measured at VDD /2
DevicetoDevice Skew (Note 7)
CycletoCycle Jitter
(Note 7)
(1, 1H)
Measured at VDD/2 on the FBK pins of the device
Measured at 66.67 MHz, loaded outputs, 15 pF load
Measured at 66.67 MHz, loaded outputs, 30 pF load
(2, 2H)
Measured at 133 MHz, loaded outputs, 15 pF load
Measured at 66.67 MHz, loaded outputs, 15 pF load
Measured at 66.67 MHz, loaded outputs, 30 pF load
PLL Lock Time (Note 7)
Stable power supply, valid clock presented on
REF and FBK pins
5. For all measurements use Test Circuit #1.
6. All parameters are specified at Commercial and Industrial temperature unless stated otherwise.
7. Parameter is guaranteed by design and characterization. Not 100% tested in production.
Min
10
12
10
12
40
45
Typ Max Unit
100 MHz
100
133
133
50 60 %
50 55 %
2.2 nS
2.5
1.5 2 nS
1.5 nS
2.2 nS
2.5
1.25 1.5 nS
1.5 nS
200 pS
200
400
0 ±250 pS
0 500 pS
180 pS
200
125
380
400
1.0 mS
http://onsemi.com
5

5 Page










PáginasTotal 8 Páginas
PDF Descargar[ Datasheet ASM5P2304A.PDF ]




Hoja de datos destacado

Número de piezaDescripciónFabricantes
ASM5P2304A3.3V Zero Delay BufferAlliance Semiconductor Corporation
Alliance Semiconductor Corporation
ASM5P2304A3.3V Zero Delay BufferON Semiconductor
ON Semiconductor
ASM5P2304B3.3V Zero Delay BufferAlliance Semiconductor Corporation
Alliance Semiconductor Corporation

Número de piezaDescripciónFabricantes
SLA6805M

High Voltage 3 phase Motor Driver IC.

Sanken
Sanken
SDC1742

12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.

Analog Devices
Analog Devices


DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.


DataSheet.es    |   2020   |  Privacy Policy  |  Contacto  |  Buscar