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PDF NCP81111 Data sheet ( Hoja de datos )
| Número de pieza | NCP81111 | |
| Descripción | 3 Phase VR12.5-6 High Speed Digital Controller | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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NCP81111
3 Phase VR12.56 High
Speed Digital Controller
with SVID and I2C
Interfaces for 5 MHz
Desktop, Notebook CPU
Applications
The NCP81111 is a high performance digital single output three
phase VR12.5−6 compatible buck solution optimized to operate at
frequencies up to 5 MHz for Intel CPU applications. The NCP81111
and can also work as a general purpose I2C controlled multiphase
voltage regulator. The NCP81111 is designed to support the
NCP81163 digital phase doubler IC which expands the capability of
the part to 6 phases for high current handling. The controller includes
true differential voltage sensing, differential current sensing, digital
input voltage feed−forward, DAC feed forward, and adaptive voltage
positioning. These features combine to provide an accurately
regulated dynamic voltage system. The control system makes use of
digital constant on time modulation and is combined with an analog
and digital current sensing system. This system provides the fastest
initial response to dynamic load events to reduced system cost. On
board user programmable memory is included for configuring the
controller’s parameters. User programmable voltage and droop
compensation is internally integrated to minimize the total board
space used. The NCP81111 is optimized for use with DRMOS.
Features
• Meets Intel®’s VR12.5 Specifications
• On Board EEPROM for User Configuration
• High Performance Digital Architecture
• Dynamic Reference Injection
• Fully Differential Voltage Current Sense Amplifiers
• “Lossless” DCR Current Sensing for Current Balancing
• Thermally Compensated Inductor Current Sensing for Droop
• User Adjustable Internal Compensation
• Switching Frequency Range of 250 kHz − 5.0 MHz
• Input Voltage Feed−forward
• Startup into Pre−Charged Loads
• Power Saving Phase Shedding
• Supports Lower Power Operation in PS3
• This is a Pb−Free Device
Applications
• Desktop, Notebook Processors, and General Purpose I2C Controlled
Multiphase Regulators.
www.onsemi.com
MARKING
DIAGRAM
1 32
QFN32
CASE 485CE
1
NCP81111
zzRr
AWLYYWWG
G
NCP81111 = Specific Device Code
zz = Configuration Option
Rr = Revision Number
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
Device*
Package Shipping†
NCP81111MNDFTXG QFN32 2500 / Tape &
(Pb−Free)
Reel
NCP81111MNzzTXG QFN32 2500 / Tape &
(Pb−Free)
Reel
*zz = Configurable Option, please contact Sales for
additional information.
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2015
November, 2015 − Rev. 4
1
Publication Order Number:
NCP81111/D
1 page  
NCP81111
VSN
VSS_SENSE
R34 100
R2 0.0
VSENSE J1312
VCC_SENSE
VSP
R3
V_1P05_VCCP VCCU R48
0.0
100
SDIO
UJ1S3B1−I2C_COMM_MODUASLLECERLKT
GND
INPUT1
SCL
SCA
+5V
SCL
SDA
ENABLE
VR_RDY
ENABLE
VR_RDY
R161
1.0K
J29 J27
JP5
12
ETCH
AGND
VDC
R40 VFF
1.0K
C82
0.01uF
AGND
J99 J100
J104
R4 0.0
R12
49.9
1000pF
C51
VR_HOT
RT22
220K
Place by phase 1 inductor
AGND
AGND
U6
AGND J92
SDA
1
SDA
24
TEST1
SCL 2
SCL
23
TEST2/ADDR1
3 22
EN CSP1
R46 J95 4
21
0k
5 TEST3/I2CADDR0 NCP81111
CSN1
20
VFF
QFN 32, 5X5mm, 0P5
CSP2
6
VDIG
19
CSN2
7
VCCD
18
CSP3
8
VCCA
17
CSN3
C89
0.01uF
C84
0.01uF
C222
10uF
SMOD3
PWM3
SMOD2
PWM2
DRON
SMOD1
PWM1
Place Near J92 an J93
J94
J9R347
0k
C94
DNP
R9
14.0K
C80
.015uF R24
C88
100pF
AGND
10.0
CSP1
CSN1
C93
DNP
R27
14.0K
C85
.015uF R22
10.0
CSP2
CSN2
C92
DNP
C86
100pF
AGND
R10
14.0K
C83
.015uF R23
10.0
CSP3
CSN3
C87
100pF
AGND
V5_CONT
R45
1
Figure 3. Three Phase Application Control Circuit
VDC
VDC
V5S
V5_DRMOS
R18
1.00
Place close
to DRMOS pins
C50
4.7uF
C268
1uF
PWM1
DRON
SMOD1
R16
0.00
VDC
V5S
V5_DRMOS
R20
1.00
Place close
to DRMOS pins
C52
4.7uF
C269
1uF
PWM3
DRON
SMOD3
R19
0.00
Place caps close to
DRMOS pins on top
C280 C281 C274
22uF 22uF 1uF
2
VCIN
3
NC
1
ZCD_EN#
39
DISB#
40
PWM
NCP5338
J133J118
Place caps close to
DRMOS pins on top
C284 C285 C277
22uF 22uF 1uF
VDC
U2 C38
PHASE
VSWH
VSWH
VSWH
VSWH
VSWH
VSWH
VSWH
VSWH
VSWH
0.1uF
7
15
43
35
34
33
32
31
30
29
L5 DNP
L3
DNP
SW1 JP19
ETCH
SW1
JP20
ETCH
R8
1.0
C146
470pF
Place close
to DRMOS pins
VCCU
CSN1
CSP1
V5S
V5_DRMOS
R14
1.00
Place close
to DRMOS pins
C44
4.7uF
C267
1uF
PWM2
DRON
SMOD2
R15
0.00
Place caps close to
DRMOS pins on top
C282 C283 C272
22uF 22uF 1uF
2
VCIN
3
NC
1
ZCD_EN#
39
DISB#
40
PWM
NCP5338
J132J117
U1 C37
PHASE
VSWH
VSWH
VSWH
VSWH
VSWH
VSWH
VSWH
VSWH
VSWH
0.1uF
7
15
43
35
34
33
32
31
30
29
L6 DNP
L2
DNP
SW2 JP17
ETCH
SW2
JP18
ETCH
R7
1.0
C145
470pF
Place close
to DRMOS pins
VCCU
CSN2
CSP2
2
VCIN
3
NC
1
ZCD_EN#
39
DISB#
40
PWM
NCP5338
J134J119
U3 C39
PHASE
VSWH
VSWH
VSWH
VSWH
VSWH
VSWH
VSWH
VSWH
VSWH
0.1uF
7
15
43
35
34
33
32
31
30
29
L7 DNP
L4
DNP
SW3 JP21
ETCH
SW3
JP22
ETCH
R21
1.0
C147
470pF
Place close
to DRMOS pins
VCCU
CSN3
CSP3
Figure 4. Three Phase Applications Power Stage Circuit
www.onsemi.com
5
5 Page 
NCP81111
For a single−byte write the sequence is as follows:
S I2C_ADDR+W
A USER_REG_WRITE
A
USER_ADDR
A D0 A P
This will insert data into the register as shown:
Working Registers
Data
Address
D0 USER_ADDR
For a multi−byte write command the sequence is as follows:
S I2C_ADDR+W A USER_REG_WRITE A USER_ADDR A D0 A D1 A D2 A ... A P
This will insert a block of data into the registers as shown:
Working Registers
Data
Address
D0 USER_ADDR
D1 USER_ADDR+1
D2 USER_ADDR+2
... ...
USER_NVM_RELOAD
This command will reload the User NVM settings from the NVM into the working registers.
The sequence is as follows:
S I2C_ADDR+W A
USER_NVM_RELOAD
AP
The command will reload all the registers at once and should complete in less than 50 ms (worst case). This can be used to
restore User settings after altering the working registers via the I2C interface. The reload is forced and does not require the
settings to be configured.
USER_NVM_WRITE
This is the primary method for writing the User NVM settings into the NVM.
The sequence is as follows:
S I2C_ADDR+W A
USER_NVM_WRITE
AP
The command will write all the current User settings from the working registers into the NVM. It should complete in less
than 988 ms (worst case, 380 ms typical case).
I2C USER_POWER CONTROL
Due to the internal construction of the device, when the EN pin goes low the internal regulators will turn off and the device
will lose its working state. Subsequently if the EN pin goes high the device will reinitialize its state from the NVM
configuration. For purposes of test and application configuration it is useful to power cycle the device without necessarily
losing state. In addition, preserving state allows the device to optionally skip NVM load and/or auto−calibration sequences
resulting in a faster startup time. To accomplish this, the USER_POWER command was added which allows the user to
Enable/Disable the device without power−cycling the part. It also allows the NVM, working registers, and auto−calibration
behavior to be modified when exiting the DISABLED state. The key to this command is the concept of a “Virtual Enable”
signal. This virtual−EN signal can be controlled via the USER_POWER command and will behave in a similar way to the actual
EN−pin, however when the virtual−EN is set low it will not completely power off the device. The internal regulators and clocks
will continue running in order to preserve device state. Note, the EN−pin must remain high at all times when using the device
in this way.
www.onsemi.com
11
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet NCP81111.PDF ] | |
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