DataSheet.es    


PDF A48P4616B Data sheet ( Hoja de datos )

Número de pieza A48P4616B
Descripción 16M x 16 Bit DDR DRAM
Fabricantes AMIC Technology 
Logotipo AMIC Technology Logotipo



Hay una vista previa y un enlace de descarga de A48P4616B (archivo pdf) en la parte inferior de esta página.


Total 30 Páginas

No Preview Available ! A48P4616B Hoja de datos, Descripción, Manual

Document Title
16M X 16 Bit DDR DRAM
Revision History
Rev. No. History
1.0 Initial issue
A48P4616B
16M X 16 Bit DDR DRAM
Issue Date
January 9, 2014
Remark
Final
(January, 2014, Version 1.0)
AMIC Technology, Corp.

1 page




A48P4616B pdf
A48P4616B
Pin Descriptions
Symbol
CK, CK
CKE
CS
RAS , CAS , WE
UDM, LDM
BA0, BA1
A0-A12
DQ
LDQS, UDQS
NC
VDDQ
VSSQ
VDD
VSS
VREF
Type
Description
Input
Input
Input
Clock: CK and CK are differential clock inputs. All address and control input signals
are sampled on the crossing of the positive edge of CK and negative edge of CK.
Output (read) data is referenced to the crossings of CK and CK (both directions of
crossing).
Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock
signals and device input buffers and output drivers. Taking CKE Low provides
Precharge Power Down and Self Refresh operation (all banks idle), or Active Power
Down (row Active in any bank). CKE is synchronous for power down entry and exit,
and for self refresh entry. CKE is asynchronous for self refresh exit. CKE must be
maintained high throughout read and write accesses. Input buffers, excluding CK,
CK and CKE are disabled during Power Down. Input buffers, excluding CKE, are
disabled during self refresh.
Chip Select: All commands are masked when CS is registered high. CS provides
for external bank selection on systems with multiple banks. CS is considered part of
the command code.
Input
Input
Input
Input
Input / Output
Input / Output
Supply
Supply
Supply
Supply
Supply
Command Inputs: RAS , CAS , WE (along with CS ) define the command being
entered.
Input Data Mask: DM is an input mask signal for write data. Input data is masked
when DM is sampled high coincident with that input data during a Write access. DM
is sampled on both edges of DQS. Although DM pins are input only, the DM loading
matches the DQ and DQS loading. During a Read, DM can be driven high, low, or
floated. LDM corresponds to the data on DQ0-DQ7; UDM corresponds to the data on
DQ8-DQ15.
Bank Address Inputs: BA0 and BA1 define to which bank an Active, Read, Write or
Precharge command is being applied. BA0 and BA1 also determines if the mode
register or extended mode register is to be accessed during a MRS or EMRS cycle.
Address Inputs: Provide the row address for Active commands, and the column
address and Auto Precharge bit for Read/Write commands, to select one location
out of the memory array in the respective bank. A10 is sampled during a Precharge
command to determine whether the Precharge applies to one bank (A10 low) or all
banks (A10 high). If only one bank is to be precharged, the bank is selected by BA0,
BA1. The address inputs also provide the op-code during a Mode Register Set
command.
Data Input/Output: Data bus.
Data Strobe: Output with read data, input with write data. Edge-aligned with read
data, centered in write data. Used to capture write data. LDQS corresponds to the
data on DQ0-DQ7; UDQS corresponds to the data on DQ8-DQ15
No Connect: No internal electrical connection is present.
DQ Power Supply: 2.5V ± 0.2V.
DQ Ground
Power Supply: 2.5V ± 0.2V.
Ground
SSTL_2 reference voltage: (VDDQ / 2) ± 1%.
(January, 2014, Version 1.0)
4 AMIC Technology, Corp.

5 Page





A48P4616B arduino
A48P4616B
Commands
Truth Tables 1a and 1b provide a reference of the commands supported by DDR SDRAM device. A verbal description of each
command follows.
Name (Function)
CS RAS CAS WE
Deselect (Nop)
HXXX
No Operation (Nop)
L HHH
Active (Select Bank And Activate Row)
L LHH
Read (Select Bank And Activate Column, And Start Read Burst) L H L H
Write (Select Bank And Activate Column, And Start Write Burst) L H L L
Burst Terminate
L HH L
Precharge (Deactivate Row In Bank Or Banks)
L LHL
Auto Refresh Or Self Refresh (Enter Self Refresh Mode)
L L LH
Mode Register Set
LLLL
Address
X
X
Bank/Row
Bank/Col
Bank/Col
X
Code
X
Op-Code
MNE
NOP
NOP
ACT
Read
Write
BST
PRE
AR/SR
MRS
Note
1, 9
1, 9
1, 3
1, 4
1, 4
1, 8
1, 5
1, 6, 7
1, 2
Note:
1. CKE is high for all commands shown except Self Refresh.
2. BA0, BA1 select either the Base or the Extended Mode Register (BA0 = 0, BA1 = 0 selects Mode Register; BA0 = 1, BA1 = 0
selects Extended Mode Register; other combinations of BA0-BA1 are reserved; A0-A12 provide the op-code to be written to
the selected Mode Register.)
3. BA0-BA1 provide bank address and A0-A12 provide row address.
4. BA0, BA1 provide bank address; A0-A8 provide column address; A10 high enables the Auto Precharge feature (non-
persistent), A10 low disables the Auto Precharge feature.
5. A10 LOW: BA0, BA1 determine which bank is precharged.
A10 HIGH: all banks are precharged and BA0, BA1 are “Don’t Care.”
6. This command is auto refresh if CKE is high; Self Refresh if CKE is low.
7. Internal refresh counter controls row and bank addressing; all inputs and I/Os are “Don’t Care” except for CKE.
8. Applies only to read bursts with Auto Precharge disabled; this command is undefined (and should not be used) for read bursts
with Auto Precharge enabled or for write bursts
9. Deselect and NOP are functionally interchangeable.
Truth Table 1b: DM Operation
Name (Function)
Write Enable
DM
L
DQs
Valid
Write Inhibit
H
X
Note: Used to mask write data; provided coincident with the corresponding data.
Note
1
1
(January, 2014, Version 1.0)
10 AMIC Technology, Corp.

11 Page







PáginasTotal 30 Páginas
PDF Descargar[ Datasheet A48P4616B.PDF ]




Hoja de datos destacado

Número de piezaDescripciónFabricantes
A48P461616M X 16 Bit DDR DRAMAMIC Technology
AMIC Technology
A48P4616B16M x 16 Bit DDR DRAMAMIC Technology
AMIC Technology

Número de piezaDescripciónFabricantes
SLA6805M

High Voltage 3 phase Motor Driver IC.

Sanken
Sanken
SDC1742

12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.

Analog Devices
Analog Devices


DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.


DataSheet.es    |   2020   |  Privacy Policy  |  Contacto  |  Buscar