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PDF GD25Q16C Data sheet ( Hoja de datos )

Número de pieza GD25Q16C
Descripción 3.3V Uniform Sector Dual and Quad Serial Flash
Fabricantes ELM 
Logotipo ELM Logotipo



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No Preview Available ! GD25Q16C Hoja de datos, Descripción, Manual

http://www.elm-tech.com
GD25Q16C
DATASHEET

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GD25Q16C pdf
GD25Q16CxIGx 3.3V Uniform Sector Dual and Quad Serial Flash
2. GENERAL DESCRIPTION
http://www.elm-tech.com
The GD25Q16C(16M-bit) Serial flash supports the standard Serial Peripheral Interface (SPI), and supports the
Dual/Quad SPI: Serial Clock, Chip Select, Serial Data I/O0 (SI), I/O1 (SO), I/O2 (WP#) and I/O3 (HOLD#).
The Dual I/O data is transferred with speed of 240Mbits/s and the Quad I/O & Quad Output data is transferred
with speed of 480Mbits/s.
Connection Diagram
8-LEAD SOP
Pin Description
Pin Name
CS#
SO (IO1)
WP# (IO2)
VSS
SI (IO0)
SCLK
HOLD# (IO3)
VCC
I/O
I
I/O
I/O
I/O
I
I/O
8-LEAD WSON
Description
Chip Select Input
Data Output (Data Input Output 1)
Write Protect Input (Data Input Output 2)
Ground
Data Input (Data Input Output 0)
Serial Clock Input
Hold Input (Data Input Output 3)
Power Supply
Block Diagram
WP#(IO2)
Write Control
Logic
HOLD#(IO3)
SCLK
CS#
SI(IO0)
SO(IO1)
SPI
Command &
Control Logic
Status
Register
High Voltage
Generators
Flash
Memory
Page Address
Latch/Counter
Column Decode And
256-Byte Page Buffer
Byte Address
Latch/Counter
49 - 5
Rev.1.0

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GD25Q16C arduino
GD25Q16CxIGx 3.3V Uniform Sector Dual and Quad Serial Flash
http://www.elm-tech.com
QE bit.
The Quad Enable (QE) bit is a non-volatile Read/Write bit in the Status Register that allows Quad operation.
When the QE bit is set to 0 (Default) the WP# pin and HOLD# pin are enable. When the QE pin is set to 1,
the Quad IO2 and IO3 pins are enabled. (The QE bit should never be set to 1 during standard SPI or Dual SPI
operation if the WP# or HOLD# pins are tied directly to the power supply or ground).
LB bit.
The LB bit is a non-volatile One Time Program (OTP) bit in Status Register (S10) that provide the write protect
control and status to the Security Registers. The default state of LB is 0, the security registers are unlocked. LB
can be set to 1 individually using the Write Register instruction. LB is One Time Programmable, once it’s set to 1,
the Security Registers will become read-only permanently.
CMP bit.
The CMP bit is a non-volatile Read/Write bit in the Status Register (S14). It is used in conjunction the BP4-
BP0 bits to provide more flexibility for the array protection. Please see the Status registers Memory Protection
table for details. The default setting is CMP=0.
HPF bit.
The High Performance Flag (HPF) bit indicates the status of High Performance Mode (HPM). When HPF bit
sets to 1, it means the device is in High Performance Mode, when HPF bit sets 0 (default), it means the device is
not in High Performance Mode.
SUS bits.
The SUS bit is a read only bit in the status register (S15) that is set to 1 after executing an Erase/Program
Suspend (75H) command. The SUS bit is cleared to 0 by Erase/Program Resume (7AH) command as well as a
power-down, power-up cycle.
49 - 11
Rev.1.0

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