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Número de pieza | NCS12802 | |
Descripción | 12-Channel I2C Programmable Gamma Voltage Reference Generator | |
Fabricantes | ON Semiconductor | |
Logotipo | ||
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No Preview Available ! NCS12802
12-Channel I2C
Programmable Gamma
Voltage Reference
Generator with Integrated
Auto-read
The NCS12802 is a 12− channel programmable voltage reference
generator providing the gamma correction references to the
TFT−LCD panel through the source driver circuit.
The twelve output voltage references are programmed through an
I2C interface which can operate at standard and high speed. The output
buffers can be finely tuned due to the 10 bit DAC precision (1024
steps). In addition, the NCS12802 features an auto−read function
which allows uploading binary data from an external EEPROM. To
support this capability, the device can act as both slave and master I2C.
In order to accelerate the dynamic correction process, the
NCS12802 has two separate register banks. It can simultaneously
store two different curves.
The NCS12802 is proposed in a QFN24 package and an operating
temperature range from −40°C to +95°C.
Features
• 12−Channel Gamma Generator
• 1024−step Resolution (10 bits)
• Dual Bank
• Rail−to−Rail Outputs
• Auto−read Function to Communicate with External EEPROM
• Two Wire Digital Programming Interface
• Low Power Supply Current of 800 mA per Channel
• Digital Power Supply from 2.3 V to 5.0 V
• Operating Voltage from 9 V to 17.5 V
• I2C Programming Interface (Standard and Fast−Speed)
• ESD Human Body Model Protection 2 kV,
Machine Model 300 V
• Operating Temperature Range: −40°C to +95°C
• Available in a QFN−24 Package with Exposed Pad
• This is a Pb−Free Device*
Typical Application
• TFT−LCD TV Panels
• LCD Monitor Panels
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
http://onsemi.com
24 PIN QFN, 4x4
MN SUFFIX
CASE 485L
MARKING
DIAGRAM
1 NCS
12802
ALYWG
G
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
Device
Package
Shipping†
NCS12802MNTXG QFN−24 3000 / Tape &
(Pb−Free)
Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2012
June, 2012 − Rev. 0
1
Publication Order Number:
NCS12802/D
1 page NCS12802
ELECTRICAL CHARACTERISTICS AVDD = +15 V, DVDD = 3.3 V, RL = 1.5 kW connected to ground, TA = 25°C, CL = 200 pF,
unless otherwise specified
Symbol
Characteristics
Conditions
Min Typ Max Unit
ANALOG
Vrst
Voh
Vol
Io
INL
DNL
DG
LReg
Reset Value
Buffer Output Swing – High
(TA = −40°C to + 95°C)
Buffer Output Swing – Low
(TA = −40°C to + 95°C)
Continuous Output Current
Integral Non−linearity
Differential Non−linearity
Gain Error
Load Regulation
TD Program to Out Delay
Tbksel Bank Switching Delay
I2C ELECTRICAL CHARACTERISTICS
All outputs set to Code 0000h
OUT1 to OUT12 – Code 03FFh – Sourcing 10 mA
OUT1 to OUT12 – Code 03FFh – Sourcing 5 mA
OUT1 to OUT12 – Code 0000h – Sinking 10 mA
OUT1 to OUT12 – Code 0000h – Sinking 5 mA
Code 3FFh
Vout = GND + 0.3 V to AVDD − 0.3 V
Vout = GND + 0.3 V to AVDD − 0.3 V
Vout = GND + 0.3 V to AVDD − 0.3 V
10 mA, All Buffers Vout = AVDD / 2,
Iout = +10 mA to −10 mA 5 mA Step
LD Pin = 0, Vout = 50% of Code 1023, AVDD = 9 V
0.015 0.12
14.7
14.8 14.9
0.15
0.075
0.25
0.15
30
0.3
0.3
0.12
0.5
2
1 3.5
V
V
V
mA
LSB
LSB
%
mV/
mA
ms
ms
FCLK
Clock Frequency
(−40°C to +95°C)
Standard/Fast Mode
High Speed Mode
400 kHz
3.4 MHz
VIL Low Level Input Voltage
SDA or SCL
0.3 x
DVDD
V
VIH High Level Input Voltage
SDA or SCL
0.7 x
DVDD
V
VOL Low Level Output Voltage
(Logic 0)
Isink = 3 mA
0.1 0.4
V
FMEM EEPROM Clock Speed
Master Mode
66 100 kHz
ANALOG POWER SUPPLY
IAVDD Analog Supply Current
Outputs at Reset Values, No load
Over temperature from −40°C to 95°C
2.8 7 mA
8
PSRR
Power Supply Rejection
Ratio
F = 70 kHz, Vac = 1 VPP on AVDD line
−75 dB
DIGITAL POWER SUPPLY
IDVDD Digital Supply Current
Outputs at Reset Values, No load, Two Wires Inactive
Over temperature from −40°C to 95°C
95 250 mA
95
DIGITAL VOLTAGE LEVELS
VIH High Level Input Voltage
(Logic 1)
0.7 x
DVDD
V
VIL Low Level Input Voltage
(Logic 0)
0.3 x
DVDD
V
Ileak
POR
Input Leakage Current
Power On Reset
±0.01 ±10
1.1 1.5 1.7
mA
V
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
7. Observe maximum power dissipation. Exposed thermal die is soldered to the PCB using thermal vias.
http://onsemi.com
5
5 Page SDA
SCL
2 ms / DIV
NCS12802
2 V / DIV
2 V / DIV
2 ms / DIV
DVDD
SDA
SCL
2 V / DIV
2 V / DIV
2 V / DIV
Figure 18. Duration of EEPROM Download
THE MASTER MODE CLOCK SPEED
The NCS12802 has its own internal clock so when it goes
into a master mode, it can generate its own clock on the SCL
line.
This frequency is specified to be typically 66 kHz with a
maximum of 100 kHz.
When the Autoread mode is activated, the communication
bus needs to be available to let the NCS12802 master I2C
initiated properly for the data upload from the EEPROM.
GENRAL CALL RESET (GCR)
The answer from the device to a general call reset
instruction is dependent on the status of the EN pin. The
command is defined in two parts: one byte for the addressing
and one byte of data for the command.
START
0 0 0 0 0 0 0 0 Ack 0 0 0 0 0 1 1 0 Ack
123456789 123456789
Figure 20. General Call Reset Command
If the EN = 0, when the device receives the GCR
command 0006h, all the output buffers will be set to their
reset value of 0.07 V (code 0000). If EN = 1 before the first
ten queries or 15 ms, then the NCS12802 will download the
EEPROM data as indicated previously.
READ AGAIN FUNCTION
When the NCS12802 is in slave mode, a read again
function can be initiated to reload data from the EEPROM
at any moment. The Read Again (RA) can be described as
below in three steps:
• Send to the device address:
♦ If A0 = 0 → 74h or 11101000b
♦ If A0 = 1 → 75h or 11101010b
The NCS12802 will acknowledge this byte.
• Program the register address 00011100 which will be
acknowledged.
Figure 19. Power Up Sequence
• Send two byte of data xxxx xxxx and xxxx xxx1 where
x are undefined bits and those bytes will be
acknowledged.
DAC OUTPUT UPDATE with LD PIN:
It needs to be understood that updating the register values
is very different than updating the DAC outputs because of
the double registered structure. Three various methods exist
to send the programmed data from the register toward the
DACs in order to obtain the desired output voltage:
Method 1: Set the LD pin to a low logic level to update each
DAC output voltage as soon as his corresponding register is
updated.
Method 2: Set the LD pin to a high logic level to allow all
the DAC output voltages to retain their respective values
during the data transfer. Then, bring the LD pin voltage low
to simultaneously update all the output buffer voltages to the
new programmed value.
Method 3 (software mode): The LD pin is maintained at a
high logic level and all 12 DACs are updated when the
master writes a ‘1’ in bit 15 of any DAC register. The update
occurs after receiving the 16 bits of data on the latest register
where this ‘1’ has been written.
BKSEL PIN
The BKSEL pin allows the selection of one of the two
integrated bank of register in the NCS12802. When the pin
is at logic low level, the BANK0 is selected. Reciprocally,
when BKSEL = 1, the BANK1 is selected.
During a software mode update of the DAC outputs
(method 3 explained above), the bank to be acquired
depends on the BKSEL state.
WRITE BOTH BANKS OF DAC REGISTERS
The writes executions are commanded through the
I2C−like bus in slave mode to both banks of registers. As
there are different register addresses for the two banks, the
BKSEL pin doesn’t affect the ‘write’ command on each of
the banks. Table 4 illustrates the non dependence of the
BKSEL pin to the write commands.
http://onsemi.com
11
11 Page |
Páginas | Total 21 Páginas | |
PDF Descargar | [ Datasheet NCS12802.PDF ] |
Número de pieza | Descripción | Fabricantes |
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