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PDF CP2104 Datasheet ( Hoja de datos )

Número de pieza CP2104
Descripción SINGLE-CHIP USB-TO-UART BRIDGE
Fabricantes Silicon Laboratories 
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CP2104 datasheet

1 Page

CP2104 pdf
CP2104
2. Electrical Characteristics
Table 1. Absolute Maximum Ratings
Parameter
Conditions
Min Typ Max Units
Ambient Temperature Under Bias
–55 — 125 °C
Storage Temperature
–65 — 150 °C
Voltage on RST, GPIO or UART Pin with respect to
GND
VIO > 2.2 V
VIO < 2.2 V
–0.3
–0.3
— 5.8
— VIO +
3.6
V
Voltage on VBUS with respect to GND
VDD > 3.0 V
VDD not powered
–0.3
–0.3
— 5.8
V
— VDD +
3.6
Voltage on VDD or VIO with respect to GND
–0.3 —
4.2
V
Maximum Total Current through VDD, VIO, and GND
— — 500 mA
Maximum Output Current Sunk by RST or any I/O
pin
— — 100 mA
Note: Stresses above those listed may cause permanent damage to the device. This is a stress rating only, and functional
operation of the devices at or exceeding the conditions in the operation listings of this specification is not implied.
Exposure to maximum rating conditions for extended periods may affect device reliability.
Table 2. Global DC Electrical Characteristics
VDD = 3.0 to 3.6 V, –40 to +85 °C unless otherwise specified.
Parameter
Conditions
Min Typ Max Units
Digital Supply Voltage (VDD)
Digital Port I/O Supply Voltage (VIO)
Voltage on VPP with respect to GND during a
ROM programming operation
VIO > 3.3 V
3.0
1.8
5.75
— 3.6
— VDD
— VIO +
3.6
V
V
V
Capacitor on VPP for ROM programming
Supply Current1
Supply Current1
Supply Current—USB Pull-up2
— 4.7 — µF
Normal Operation;
17.0 18.5
mA
VREG Enabled
Suspended;
VREG Enabled
— 100 200 µA
— 200 228 µA
Specified Operating Temperature Range
–40 — +85 °C
Notes:
1. If the device is connected to the USB bus, the USB Pull-up Current should be added to the supply current for total
supply current.
2. The USB Pull-up supply current values are calculated values based on USB specifications.
Rev. 1.1
5

5 Page

CP2104 arduino
CP2104
Figure 4. QFN-24 Recommended PCB Land Pattern
Table 9. QFN-24 PCB Land Pattern Dimensions
Dimension
Min
Max
Dimension
Min
C1 3.90 4.00
C2 3.90 4.00
E 0.50 BSC
X1 0.20 0.30
X2 2.70
Y1 0.65
Y2 2.70
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This Land Pattern Design is based on the IPC-7351 guidelines.
Max
2.80
0.75
2.80
Solder Mask Design
3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder
mask and the metal pad is to be 60 m minimum, all the way around the pad.
Stencil Design
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used
to assure good solder paste release.
5. The stencil thickness should be 0.125 mm (5 mils).
6. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
7. A 2x2 array of 1.10 mm x 1.10 mm openings on a 1.30 mm pitch should be used for the center
pad.
Card Assembly
8. A No-Clean, Type-3 solder paste is recommended.
9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small
Body Components.
Rev. 1.1
11

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