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PDF SAMG55J Data sheet ( Hoja de datos )

Número de pieza SAMG55J
Descripción SMART ARM-based Flash MCU
Fabricantes ATMEL Corporation 
Logotipo ATMEL Corporation Logotipo



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SAM G55G / SAM G55J
Atmel | SMART ARM-based Flash MCU
DATASHEET
Description
The Atmel® | SMART SAM G55 is a series of Flash microcontrollers based on the
high-performance 32-bit ARM® Cortex®-M4 RISC processor with FPU (Floating
Point Unit). It operates at a maximum speed of 120 MHz and features 512 Kbytes
of Flash and up to 176 Kbytes of SRAM. The peripheral set includes eight flexible
communication units comprising USARTs, SPIs and I2C-bus interfaces (TWIs),
two three-channel general-purpose 16-bit timers, two I2S controllers, one-channel
pulse density modulation, one 8-channel 12-bit ADC, one real-time timer (RTT)
and one real-time clock (RTC), both located in the ultra low-power backup area.
The Atmel | SMART SAM G55 devices have three software-selectable low-power
modes: Sleep, Wait and Backup. In Sleep mode, the processor is stopped while
all other functions can be kept running. In Wait mode, all clocks and functions are
stopped but some peripherals can be configured to wake up the system based on
events, including partial asynchronous wake-up (SleepWalking™). In Backup
mode, RTT, RTC and wakeup logic are running.
For power consumption optimization, the flexible clock system offers the capability
of having different clock frequencies for some peripherals. Moreover, the
processor and bus clock frequency can be modified without affecting the
peripheral processing.
The real-time event management allows peripherals to receive, react to and send
events in Active and Sleep modes without processor intervention.
The SAM G55 devices are general-purpose low-power microcontrollers that offer
high performance, processing power and small package options combined with a
rich and flexible peripheral set. With this unique combination of features, the SAM
G55 series is suitable for a wide range of applications including consumer,
industrial control and PC peripherals.
The device operates from 1.62V to 3.6V and is available in three packages:
49-pin WLCSP, 64-pin QFN and 64-pin LQFP.
Atmel-11289E-ATARM-SAM-G55G-SAM-G55J-Datasheet_30-Nov-15

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SAMG55J pdf
2. Block Diagram
Figure 2-1. SAM G55 Block Diagram
TST
PCK[2:0]
ERASE
WKUP[15:0]
XIN32
XOUT32
XIN
XOUT
VDDIO
NRST
VDDCORE
VUSB
(64pins ONLY)
PLLA
PLLUSB
RC OSC
8/16/24 MHz
Power
Management
Controller
Backup area
Supply
Controller
Tamper Detection
32K OSC
32K RC
Power-on
Reset
Real-time
Clock
256-bit
General-purpose
Backup Registers
Real-time
Timer
Watchdog
Timer
Reset
Controller
Supply
Monitor
PIOA/PIOB
System Controller
JTAG and Serial Wire
Voltage
Regulator
In-Circuit Emulator
Cortex-M4 Processor
fMAX 120 MHz
DSP
NVIC
24-bit SysTick
Counter
MPU
FPU
ID
S
CMCC
SRAM
2/4/8 KB Cache Up to 16 Kbytes
MM
4-layer AHB Bus Matrix
fMAX 120 MHz
S MM
S
S
MS
Flash
Unique
Identifier
User
Signature
Flash
512 Kbytes
SRAM
160 Kbytes
ROM
8 Kbytes
AHB/APB
Bridge
PDC
CRCCU
DMA
USB OHCI
PDMIC_DAT
PDMIC_CLK
I2SCK0...1
I2SWS0...1
I2SDI0...1
I2SDO0...1
I2SMCK0...1
SCK_SPCK0...7
TXD_MOSI_TWD0...7
RXD_MISO_TWCK0...7
RTS_NPCS1_0...7
CTS_NPCS0NSS_0...7
PDC
PDMIC0
PDMIC1 PDC
PDC
2 x I2SC
FLEXCOM
PDC
8x
USART, SPI, TWI
2668
bytes
USB 2.0
FIFO Full-speed
DP
DM
AD[7:0]
ADTRG
PDC
12-bit ADC
Timer Counter A
TC[0..2]
Timer Counter B
TC[3..5]
TCLK[2:0]
TIOA[2:0]
TIOB[2:0]
SAMG55 [DATASHEET]
Atmel-11289E-ATARM-SAM-G55G-SAM-G55J-Datasheet_30-Nov-15
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SAMG55J arduino
5. Power Considerations
5.1 Power Supplies
The SAM G55 has the following power supply pins:
VDDCORE pins: Power the core, including the processor, the embedded memories and the peripherals,
except the RTC, RTT, and Supply controller (SUPC). It is recommended to connect VDDCORE to VDDOUT.
VDDIO pins: Power the peripheral I/O lines, RTC, RTT, and SUPC peripherals, voltage regulator and ADC;
voltage ranges from 1.62V to 3.6V.
VDDUSB pins: Power the USB (only for devices with 64-pin package), voltage ranges from 3.0V to 3.6V.
The ground pins GND are common to VDDCORE and VDDIO.
5.2 Power-up Considerations
In order to prevent any overcurrent at power-up, it is recommended to connect pin ADVREF to VDDIO, or to get
ADVREF to rise as much as possible at the same time as VDDIO.
Note: Pin ADVREF is only available on 64-pin packages QFN and LQFP.
5.2.1
VDDIO Versus VDDCORE
VDDIO must always be higher than or equal to VDDCORE.
VDDIO must reach its minimum operating voltage (1.62 V) before VDDCORE has reached VDDCOREXT(min). The
minimum slope for VDDCORE is defined by (VDDCOREXT(min) - VTH+) / tRES.
If VDDCOREXT rises at the same time as VDDIO, the VDDIO rising slope must be higher than or equal to 7V/ms.
If VDDCORE is powered by the internal regulator, all power-up considerations are met.
Figure 5-1.
VDDCORE and VDDIO Constraints at Startup
Supply (V)
VDDIO(min)
V
DDCORE(min)
VTH+
VDDIO
VDDCORE
Core supply POR output
Time (t)
tRES
SLCK
At power-down, there is no constraint on VDDCORE and VDDIO as the regulator must be enabled.
SAMG55 [DATASHEET]
Atmel-11289E-ATARM-SAM-G55G-SAM-G55J-Datasheet_30-Nov-15
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