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PDF UPD9993 Data sheet ( Hoja de datos )

Número de pieza UPD9993
Descripción PCM SOUND GENERATOR AND MP3/AAC DECODER LSI
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DATA SHEET
MOS INTEGRATED CIRCUIT
µPD9993
PCM SOUND GENERATOR AND MP3/AAC DECODER LSI
(WITH REAL-TIME SURROUND)
FOR MOBILE PHONES
DESCRIPTION
The µ PD9993 is a PCM sound generator and MP3/AAC decoder LSI that includes an on-chip wide real-time
surround function for mobile phones.
FEATURES
PCM sound generation method provides realistic sound reproduction
• Built-in digital signal processor for MP3/AAC decoder
• Built-in real-time wide surround function
(for all sources including PCM sound generators, MP3/AAC sources, and audio serial input)
• Up to 68 tones (= 64 polyphonic tones + 4 ADPCM) can be played at the same time, so an abundant variety of
tunes can be generated and played
• Supports ADPCM playback. Simultaneous playback with MIDI is also enabled
• Includes a high-performance D/A converter with 16-bit resolution
• Supports five sampling frequency modes: 8 kHz, 16 kHz, 32 kHz, 44.1 kHz, and 48 kHz (ASI and MP3/AAC
decoder)
• Provides audio serial I/O interface (16 bits). The serial data input frequency is variable between 32 fs and 64 fs
(during slave mode). Supported formats are right-justified, left-justified, and IIS.
• Includes function for mixing MIDI/ADPCM/MP3/AAC signals and audio serial input signals (only fs = 32 kHz
sampling is supported).
• Supports 8-bit parallel interface. The host CPU is connected via an 8-bit parallel interface when PS = 0.
• Supports SPI. The host CPU is connected via a 3-wire or a 4-wire serial peripheral interface (SPI) when PS = 1.
• Supports three outputs modes (single end MONO, differential MONO, and STEREO)
• Includes output control functions for vibrator and LED
• Built-in PLL, so various types of input clocks can be supported
• Supports two I/O power supply voltages: 1.8 to 3 V (supports only digital pins)
• Power supply voltages:
DVDD: 1.425 to 1.575 V
EVDD: 1.71 to 3.3 V
AVDD: 2.7 to 3.3 V
AVDD_P: 2.7 to 3.3 V
• 85-pin tape FBGA package (6 × 6 mm body size, 0.5 mm ball pitch)
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. S17306EJ2V0DS00 (2nd edition)
Date Published December 2004 NS CP (K)
Printed in Japan
The mark shows major revised points.
2004

1 page




UPD9993 pdf
µ PD9993
CONTENTS
1. PIN FUNCTIONS......................................................................................................................................8
1.1 Pin Configuration............................................................................................................................8
1.2 Explanation of Pin Functions ........................................................................................................9
1.3 Connection of Unused Pins.........................................................................................................14
1.4 Initial State of Pins........................................................................................................................14
1.5 Pin Status ......................................................................................................................................15
2. GENERAL DESCRIPTION ....................................................................................................................18
2.1 Block Diagram...............................................................................................................................18
3. HOST CPU INTERFACE.......................................................................................................................20
3.1 Parallel I/F Mode............................................................................................................................20
3.1.1 Write access .......................................................................................................................................20
3.1.2 Read access.......................................................................................................................................22
3.2 Serial I/F Mode...............................................................................................................................24
3.2.1 Access format in 3-wire SPI mode......................................................................................................25
3.2.2 Access format in 4-wire SPI mode......................................................................................................28
3.2.3 Initialization signal for serial I/F ..........................................................................................................31
4. AUDIO SERIAL INTERFACE.................................................................................................................32
5. ADPCM INPUT INTERFACE .................................................................................................................34
5.1 CLK8K ............................................................................................................................................34
5.2 TRSCK and RDATA........................................................................................................................34
5.2.1 Serial recording interface....................................................................................................................34
6. MP3/AAC DECODER ............................................................................................................................35
6.1 Interface .........................................................................................................................................35
6.2 Firmware ........................................................................................................................................35
6.2.1 Procedure for downloading firmware for MP3/AAC decoder............................................................... 35
6.3 Interrupts .......................................................................................................................................36
7. REGISTERS............................................................................................................................................37
7.1 Parallel I/F Mode............................................................................................................................37
7.1.1 Register map for chip control..............................................................................................................37
7.1.2 Register map for DSP (MP3/AAC decoder)........................................................................................38
7.2 Serial I/F Mode...............................................................................................................................39
7.2.1 Sound generator bank ........................................................................................................................39
7.2.2 Chip control bank ...............................................................................................................................40
7.2.3 DSP bank ...........................................................................................................................................41
7.3 Detailed Description of DSP (DSP Bank) Registers ..................................................................42
7.3.1 Command reset of DSP (HRST) ........................................................................................................42
7.3.2 Command reset of HIO (HIORSTB) ...................................................................................................42
7.3.3 Command reset of DSP latch (DRSTB)..............................................................................................42
7.3.4 Clock signal control register for DSP block (CLKE) ............................................................................43
7.3.5 Firmware download enable register (MWDNEN)................................................................................43
Data Sheet S17306EJ2V0DS
5

5 Page





UPD9993 arduino
µ PD9993
(3) Host interface pins
Pin Name
WR_B/ SCLK
Pin No.
7K
D0/ SERINIT
8K
D1 to D7
8J, 10H, 9H,
10G, 9G, 10F, 9F
INT_SG_B
10E
INT_DSP_B
8F
PS 6B
I/O
Input
I/O
I/O
Output
output
Input
(2/2)
Function
1. Parallel I/F mode (when PS = 0)
Host write input
This pin is set as active (low) while the host CPU writes to a host interface
register.
Do not set this pin and the RD_B pin as active at the same time.
2. Serial I/F mode (when PS = 1)
Clock for serial I/F
1. Parallel I/F mode (when PS = 0)
Bit 0 for 8-bit host data bus
When the host CPU accesses the µ PD9993, address and data I/O is
performed. When the CS_B signal is inactive (high), this pin is set to high
impedance.
2. Serial I/F mode (when PS = 1)
Initialization signal for serial I/F
1. Parallel I/F mode (when PS = 0)
Bits 7-0 for 8-bit host data bus
When the host CPU accesses the µ PD9993, address and data I/O is
performed. When the CS_B signal is inactive (high), this bus is set to high
impedance.
2. Serial I/F mode (when PS = 1)
This bus is always set to high impedance. Connect these pins to GND.
Interrupt request from PCM sound generator
This signal requests interrupt from the µ PD9993 to the host CPU.
This is used when requesting data transfer or internal status notification.
Interrupt request from DSP (MP3/AAC decoder)
This signal request interrupt from the µ PD9993 to the host CPU.
This is used when requesting data transfer or internal status notification.
Parallel/serial I/F mode setting
1: Serial I/F mode
0: Parallel I/F mode
This pin has an internal pull-down resister (50 k)
(4) Exterior LED, Vibrator control output pins
Pin Name
LED
Pin No.
10C
VIB 9D
I/O
Output
Output
Function
External LED control output
This is the port output pin. Settings are entered by writing values to the port
setting register from the host CPU. Leave this pin open when not used.
External vibrator control output
This is the port output pin. Settings are entered by writing values to the port
setting register from the host CPU. Leave this pin open when not used.
Data Sheet S17306EJ2V0DS
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