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PDF PL663-08 Data sheet ( Hoja de datos )

Número de pieza PL663-08
Descripción Analog Frequency Multiplier
Fabricantes Micrel 
Logotipo Micrel Logotipo



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Analog Frequency Multiplier
PL663-xx XO Families
DESCRIPTION
Analog Frequency Multipliers TM (AFMs) are the
industry’s first “Balanced Oscillatorutilizing analog
multiplication of the fundamental frequency (at
double or quadruple frequency), combined with an
attenuation of the fundamental of the reference
crystal, without using a phase-locked loop (PLL), in
CMOS technology.
Patent pending PL663-xx family of AFM products
can achieve up to 800 MHz differential LVPECL,
LVDS, or single-ended LVCMOS output with little
jitter or phase noise deterioration.
PL663-xx family of products utilizes a low-power
CMOS technology and is housed in GREEN/ RoHS
compliant 16-pin TSSOP and 3x3 QFN packages.
FEATURES
Non-PLL frequency multiplication
Input frequency from 30-200 MHz
Output frequency from 60-800 MHz
Low phase noise and jitter (equivalent to fundamental
at the output frequency)
Ultra-low jitter
o RMS phase jitter < 0.25 ps (12 kHz to 20 MHz)
o RMS period jitter < 2.5 ps typ.
Low phase noise
o -145 dBc/Hz @ 100 kHz offset from 155.52 MHz
o -150 dBc/Hz @ 10 MHz offset from 155.52 MHz
Low input frequency eliminates the need for expensive
crystals
Differential LVPECL/LVDS, or single-ended LVCMOS
output
Single 2.5V or 3.3V +/- 10% power supply
Optional industrial temperature range (-40C to
+85C)
Available in 16-pin GREEN/RoHS compliant TSSOP,
and 16-pin 3x3 QFN packages.
Figure 1: 2X AFM Phase Noise at 212.5 MHz (106.25 MHz 3rd overtone crystal)
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944-0800 • fax +1(408) 474-1000 • www.micrel.com Rev. 02/18/10 Page 1

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PL663-08 pdf
Analog Frequency Multiplier
PL663-xx XO Families
EXTERNAL COMPONENT VALUES
INDUCTOR VALUE OPTIMIZATION
The required inductor value(s) for the best performance depends on the operating frequency, and the board
layout specifications. The listed values in this datasheet are based on the calculated parasitic values from
Micrel’s evaluation board design. These inductor values provide the user with a starting point to determine the
optimum inductor values. Additional fine-tuning may be required to determine the optimal solution.
To assist with the inductor value optimization, Micrel has developed the “AFM Tuning Assistant” software. You
can download this software from Micrel’s web site (www.micrel.com). The software consists of two worksheets.
The first worksheet (named L2) is used to fine-tune the ‘L2’ inductor value, and the second worksheet (named L4)
is used for fine tuning of the ‘L4’ (used in 4x AFMs only) inductor value.
For those designs using Micrel’s recommended board layout, you can use the “AFM Tuning Assistant” to
determine the optimum values for the required inductors. This software is developed based on the parasitic
information from Micrel’s board layout and can be used to determine the required inductor and parallel capacitor
(see LWB1 and Cstray parameters) values. For those employing a different board layout in their design, we
recommend to use the parasitic information of their board layout to calculate the optimized inductor values.
Please use the following fine tuning procedure:
Figure 5: Diagram Representation of the Related System Inductance and Capacitance
DIE SIDE
- Cinternal = Based on AFM Device
- Cpad = 2.0 pF, Bond pad and its ESD circuitry
- C11 = 0.4 pF, The following amplifier stage
PCB side
- LWB1 = 2 nH, (2 places), Stray inductance
- Cstray = 1.0 pF, Stray capacitance
- L2X = 2x inductor
- C2X = range (0.1 to 2.7), Fine tune inductor if used
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944-0800 • fax +1(408) 474-1000 • www.micrel.com Rev. 02/18/10 Page 5

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PL663-08 arduino
Analog Frequency Multiplier
PL663-xx XO Families
BOARD DESIGN AND LAYOUT CONSIDERATIONS
L2X: Reduce the PCB trace inductance to a
minimum by placing L2X as physically close to their
respective pins as possible. Also be sure to bypass
each VDD connection especially taking care to place
a 0.01 uF bypass at the VDD side of L2X (see
recommended layout).
used, feed each bypass cap with its own via. Be
sure to connect any ground pin including the bypass
caps with short via connection to the ground plane.
OESEL: J1 is recommended so the same PCB
layout can be used for both OESEL settings.
Crystal Connections: Be sure to keep the ground
plane under the crystal connections continuous so
that the stray capacitace is consistent on both
crystal connections. Also be sure to keep the crystal
connections symmetrical with respect to one another
and the crystal connection pins of the IC. If you
chose to use a series capacitance and/or inductor to
fine tune the crystal frequency, be sure to put
symmetrical pads for this cap on both crystal pins
(see Cadj in recommended layout), even if one of
the capacitors will be a 0.01 uF and the other is
used to tune the frequency. To further maintain a
symmetrical balance on a crystal that may have
more internal Cstray on one pin or the other, place
capacitor pads (Cbal) on each crystal lead to ground
(see recommended layout). R3rd is only required if
a 3rd overtone crystal is used.
VDD and GND: Bypass VDDANA and VDDBUF with
separate bypass capacitors and if a VDD plane is
PL663 (2x AFM) TSSOP Layout
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944-0800 • fax +1(408) 474-1000 • www.micrel.com Rev. 02/18/10 Page 11

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