AT89LP51RD2 Hoja de datos PDF

PDF AT89LP51RD2 Datasheet ( Hoja de datos )

Número de pieza AT89LP51RD2
Descripción 8-bit Microcontroller
Fabricantes ATMEL 
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AT89LP51RD2 datasheet

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AT89LP51RD2 pdf
AT89LP51RD2/ED2/ID2 Summary - Preliminary
Table 1-1. Atmel AT89LP51RD2/ED2/ID2 Pin Description
Pin Number
Type Description
I/O P0.2: User-configurable I/O Port 0 bit 2.
35 41 37 P0.2 I/O AD2: External memory interface Address/Data bit 2.
I ADC2: ADC analog input 2.
I/O P0.1: User-configurable I/O Port 0 bit 1.
36 42 38 P0.1 I/O AD1: External memory interface Address/Data bit 1.
I ADC1: ADC analog input 1.
I/O P0.0: User-configurable I/O Port 0 bit 0.
37 43 39 P0.0 I/O AD0: External memory interface Address/Data bit 0.
I ADC0: ADC analog input 0.
38 44 40 VDD
I Supply Voltage
39 1
P4.2: User-configurable I/O Port 4bit 2.
XTAL2B: Output from low-frequency inverting oscillator amplifier B (AT89LP51ID2 only). It may
be used as a port pin if the internal RC oscillator or external clock is selected as the clock
P1.0: User-configurable I/O Port 1 bit 0.
40 2
I/O T2: Timer 2 External Input or Clock Output.
I/O XTAL1B: Input to the low-frequency inverting oscillator amplifier B and internal clock generation
circuits. It may be used as a port pin if the internal RC oscillator is selected as the clock source.
41 3
I/O P1.1: User-configurable I/O Port 1 bit 1.
2 P1.1
I T2EX: Timer 2 External Capture/Reload Input.
I SS: SPI Slave-Select.
42 4
I/O P1.2: User-configurable I/O Port 1 bit 2.
43 5
I/O P1.3: User-configurable I/O Port 1 bit 3.
I/O CEX0: Capture/Compare external I/O for PCA module 0.
I/O P1.4: User-configurable I/O Port 1 bit 4.
6 5 P1.4 I SS: SPI Slave-Select (Remap Mode). This pin is an input for In-System Programming
I/O CEX1: Capture/Compare external I/O for PCA module 1.
1. The AT89LP51ID2 is not available in the PDIP package.
2. Overview
The Atmel® AT89LP51RD2/ED2/ID2 is a low-power, high-performance CMOS 8-bit 8051 micro-
controller with 64KB of In-System Programmable Flash program memory. The AT89LP51ED2
and AT89LP51ID2 provide an additional 4KB of EEPROM for nonvolatile data storage. The
devices are manufactured using Atmel's high-density nonvolatile memory technology and are
compatible with the industry-standard 80C51 instruction set.
The AT89LP51RD2/ED2/ID2 is built around an enhanced CPU core that can fetch a single byte
from memory every clock cycle. In the classic 8051 architecture, each fetch requires 6 clock
cycles, forcing instructions to execute in 12, 24 or 48 clock cycles. In the
AT89LP51RD2/ED2/ID2 CPU, standard instructions need only one to four clock cycles providing
six to twelve times more throughput than the standard 8051. Seventy percent of instructions
need only as many clock cycles as they have bytes to execute, and most of the remaining
instructions require only one additional clock. The enhanced CPU core is capable of 20 MIPS
throughput whereas the classic 8051 CPU can deliver only 4 MIPS at the same current con-
sumption. Conversely, at the same throughput as the classic 8051, the new CPU core runs at a
much lower speed and thereby greatly reducing power consumption and EMI. The

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AT89LP51RD2 arduino
A common prescaler is available to divide the time base for Timer 0, Timer 1, Timer 2 and the
WDT. The TPS3-0 bits in the CLKREG SFR control the prescaler. In Compatibility mode TPS3-0
defaults to 0101B, which causes the timers to count once every machine cycle. The counting
rate can be adjusted linearly from the system clock rate to 1/16 of the system clock rate by
changing TPS3-0. In Fast mode TPS3-0 defaults to 0000B, or the system clock rate. TPS does not
affect Timer 2 in Clock Out or Baud Generator modes.
In Compatibility mode the sampling of the external Timer/Counter pins: T0, T1, T2 and T2EX;
and the external interrupt pins, INT0 and INT1, is also controlled by the prescaler. In Fast mode
these pins are always sampled at the system clock rate.
Both Timer 0 and Timer 1 can toggle their respective counter pins, T0 and T1, when they over-
flow by setting the output enable bits in TCONB.
Interrupt Handling
Fast mode allows for faster interrupt response due to the shorter instruction execution times.
Keyboard Interface
The AT89LP51RD2/ED2/ID2 does not clear the keyboard flag register (KBF) after a read. Each
bit must be cleared in software. This allows the interrupt to be generate once per flag when mul-
tiple flags are set, if desired. To mimic the old behavior the service routine must clear the whole
The keyboard can also support general edge-triggered interrupts with the addition of the
KBMOD register.
Serial Port
The timer prescaler increases the range of achievable baud rates when using Timer 1 to gener-
ate the baud rate in UART Modes 1 or 3, including an increase in the maximum baud rate
available in Compatibility mode. Additional features include automatic address recognition and
framing error detection.
The shift register mode (Mode 0) has been enhanced with more control of the polarity, phase
and frequency of the clock and full-duplex operation. This allows emulation of master serial
peripheral (SPI) and two-wire (TWI) interfaces.
I/O Ports
The P0, P1, P2 and P3 I/O ports of the AT89LP51RD2/ED2/ID2 may be configured in four differ-
ent modes. The default setting depends on the Tristate-Port User Fuse. When the fuse is set all
the I/O ports revert to input-only (tristated) mode at power-up or reset. When the fuse is not
active, ports P1, P2 and P3 start in quasi-bidirectional mode and P0 starts in open-drain mode.
P4 always operates in quasi-bidirectional mode. P0 can be configured to have internal pull-ups
by placing it in quasi-bidirectional or output modes. This can reduce system cost by removing
the need for external pull-ups on Port 0.
The P4.4–P4.7 pins are additional I/Os that replace the normally dedicated ALE, PSEN, XTAL1
and XTAL2 pins of the AT89C51RD2/ED2/ID2. These pins can be used as additional I/Os
depending on the configuration of the clock and external memory.
10 AT89LP51RD2/ED2/ID2 Summary - Preliminary

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