DataSheet.es AT89LP52 Hoja de datos PDF



PDF AT89LP52 Datasheet ( Hoja de datos )

Número de pieza AT89LP52
Descripción 8-bit Microcontroller
Fabricantes ATMEL 
Logotipo ATMEL Logotipo
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Total 30 Páginas
		
AT89LP52 datasheet

1 Page

AT89LP52 pdf
AT89LP51/52
Table 1-1. AT89LP51/52 Pin Description
Pin Number
TQFP PLCC PDIP VQFN Symbol Type
21
27
24
21
P2.3
I/O
O
22
28
25
22
P2.4
I/O
O
23
29
26
23
P2.5
I/O
O
24
30
27
24
P2.6
I/O
O
25
31
28
25
P2.7
I/O
O
26
32
29
26
P4.5
I/O
O
27
33
30
27
P4.4
I/O
O
28 34
28
NC
29 35 31 29 POL
I
30
36
32
30
P0.7
I/O
I/O
31
37
33
31
P0.6
I/O
I/O
32
38
34
32
P0.5
I/O
I/O
33
39
35
33
P0.4
I/O
I/O
34
40
36
34
P0.3
I/O
I/O
35
41
37
35
P0.2
I/O
I/O
36
42
38
36
P0.1
I/O
I/O
37
43
39
37
P0.0
I/O
I/O
38 44 40 38 VDD
I
39 1
39
NC
40 2
1
40
P1.0
I/O
I/O
41 3
2
41
P1.1
I/O
I
42 4
3 42 P1.2 I/O
43 5
4 43 P1.3 I/O
44 6
5 44 P1.4 I/O
Description
P2.3: I/O Port 2 bit 3.
A11: External memory interface Address bit 11.
P2.4: I/O Port 2 bit 5.
A12: External memory interface Address bit 12.
P2.5: I/O Port 2 bit 5.
A13: External memory interface Address bit 13.
P2.6: I/O Port 2 bit 6.
A14: External memory interface Address bit 14.
P2.7: I/O Port 2 bit 7.
A15: External memory interface Address bit 15.
P4.5: I/O Port 4 bit 5.
PSEN: External memory interface Program Store Enable (active-low).
P4.4: I/O Port 4 bit 4.
ALE: External memory interface Address Latch Enable.
Not internally connected
POL: Reset polarity (See “External Reset” on page 33.)
P0.7: I/O Port 0 bit 7.
AD7: External memory interface Address/Data bit 7.
P0.6: I/O Port 0 bit 6.
AD6: External memory interface Address/Data bit 6.
P0.5: I/O Port 0 bit 5.
AD5: External memory interface Address/Data bit 5.
P0.4: I/O Port 0 bit 4.
AD4: External memory interface Address/Data bit 4.
P0.3: I/O Port 0 bit 3.
AD3: External memory interface Address/Data bit 3.
P0.2: I/O Port 0 bit 2.
AD2: External memory interface Address/Data bit 2.
P0.1: I/O Port 0 bit 1.
AD1: External memory interface Address/Data bit 1.
P0.0: I/O Port 0 bit 0.
AD0: External memory interface Address/Data bit 0.
Supply Voltage
Not internally connected
P1.0: I/O Port 1 bit 0.
T2: Timer 2 External Input or Clock Output.
P1.1: I/O Port 1 bit 1.
T2EX: Timer 2 External Capture/Reload Input.
P1.2: I/O Port 1 bit 2.
P1.3: I/O Port 1 bit 3.
P1.4: I/O Port 1 bit 4.
3709D–MICRO–12/11
5

5 Page

AT89LP52 arduino
2.3.5
2.3.6
2.3.7
2.3.8
2.3.9
Interrupt Handling
With the addition of the IPH register, the AT89LP51/52 provides four levels of interrupt priority
for greater flexibility in handling multiple interrupts. Also, Fast mode allows for faster interrupt
response due to the shorter instruction execution times.
Serial Port
The timer prescaler increases the range of achievable baud rates when using Timer 1 to gener-
ate the baud rate in UART Modes 1 or 3, including an increase in the maximum baud rate
available in Compatibility mode. Additional features include automatic address recognition and
framing error detection.
The shift register mode (Mode 0) has been enhanced with more control of the polarity, phase
and frequency of the clock and full-duplex operation. This allows emulation of master serial
pheriperal (SPI) and two-wire (TWI) interfaces.
I/O Ports
The P0, P1, P2 and P3 I/O ports of the AT89LP51/52 may be configured in four different modes.
The default setting depends on the Tristate-Port User Fuse (See Section 17.7 on page 86).
When the fuse is set all the I/O ports revert to input-only (tristated) mode at power-up or reset.
When the fuse is not active, ports P1, P2 and P3 start in quasi-bidirectional mode and P0 starts
in open-drain mode. P4 always operates in quasi-bidirectional mode. P0 can be configured to
have internal pull-ups by placing it in quasi-bidirectional or output modes. This can reduce sys-
tem cost by removing the need for external pull-ups on Port 0.
The P4.4–P4.7 pins are additional I/Os that replace the normally dedicated ALE, PSEN, XTAL1
and XTAL2 pins of the AT89S51/52. These pins can be used as additional I/Os depending on
the configuration of the clock and external memory.
Security
The AT89LP51/52 does not support the extenal access pin (EA). Therefore it is not possible to
execute from external program memory in address range 0000H–1FFFH. When the third Lockbit
is enabled (Lock Mode 4) external program execution is disabled for all addresses above
1FFFH. This differs from AT89S51/52 where Lock Mode 4 prevents EA from being sampled low,
but may still allow external execution at addresses outside the 8K internal space.
Programming
The AT89LP51/52 supports a richer command set for In-System Programming (ISP). Existing
AT89S51/52 programmers should be able to program the AT89LP51/52 in byte mode. In page
mode the AT89LP51/52 only supports programming of a half-page of 64 bytes and therefore
requires an extra address byte as compared to AT89S51/52. Furthermore the device signature
is located at addresses 0000H, 0001H and 0003H instead of 0000H, 0100H and 0200H.
Table 2-3. Compatibility Mode versus Fast Mode Summary
Feature
Compatibility
Instruction Fetch in System Clocks
3
Instruction Execution Time in System Clocks
6, 12, 18 or 24
Default System Clock Divisor
2
Default Timer Prescaler Divisor
6
Fast
1
1, 2, 3, 4 or 5
1
1
10 AT89LP51/52
3709D–MICRO–12/11

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