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PDF AT89LP52 Datasheet ( Hoja de datos )

Número de pieza AT89LP52
Descripción 8-bit Microcontroller
Fabricantes ATMEL 
Logotipo ATMEL Logotipo

Total 30 Páginas
		
AT89LP52 Hoja de datos, Descripción, Manual
Features
8-bit Microcontroller Compatible with 8051 Products
Enhanced 8051 Architecture
– Single Clock Cycle per Byte Fetch
– 12 Clock per Machine Cycle Compatibility Mode
– Up to 20 MIPS Throughput at 20 MHz Clock Frequency
– Fully Static Operation: 0 Hz to 20 MHz
– On-chip 2-cycle Hardware Multiplier
– 256 x 8 Internal RAM
– External Data/Program Memory Interface
– Dual Data Pointers
– 4-level Interrupt Priority
Nonvolatile Program and Data Memory
– 4K/8K Bytes of In-System Programmable (ISP) Flash Program Memory
– 256 Bytes of Flash Data Memory
– 256-byte User Signature Array
– Endurance: 10,000 Write/Erase Cycles
– Serial Interface for Program Downloading
– 64-byte Fast Page Programming Mode
– 3-level Program Memory Lock for Software Security
– In-Application Programming of Program Memory
Peripheral Features
– Three 16-bit Timer/Counters with Clock Out Modes
– Enhanced UART
• Automatic Address Recognition
• Framing Error Detection
• SPI and TWI Emulation Modes
– Programmable Watchdog Timer with Software Reset and Prescaler
Special Microcontroller Features
– Brown-out Detection and Power-on Reset with Power-off Flag
– Selectable Polarity External Reset Pin
– Low Power Idle and Power-down Modes
– Interrupt Recovery from Power-down Mode
– Internal 1.8432 MHz Auxiliary Oscillator
I/O and Packages
– Up to 36 Programmable I/O Lines
– Green (Pb/Halide-free) Packages
• 40-lead PDIP
• 44-lead TQFP/PLCC
• 44-pad VQFN/MLF
– Configurable Port Modes (per 8-bit port)
• Quasi-bidirectional (80C51 Style)
• Input-only (Tristate)
• Push-pull CMOS Output
• Open-drain
Operating Conditions
– 2.4V to 5.5V VCC Voltage Range
– -40° C to 85°C Temperature Range
– 0 to 20 MHz @ 2.4V–5.5V
– 0 to 25 MHz @ 4.5V–5.5V
8-bit
Microcontroller
with 4K/8K
Bytes In-System
Programmable
Flash
AT89LP51
AT89LP52
3709D–MICRO–12/11

1 page

AT89LP52 pdf
AT89LP51/52
Table 1-1. AT89LP51/52 Pin Description
Pin Number
TQFP PLCC PDIP VQFN Symbol Type
21
27
24
21
P2.3
I/O
O
22
28
25
22
P2.4
I/O
O
23
29
26
23
P2.5
I/O
O
24
30
27
24
P2.6
I/O
O
25
31
28
25
P2.7
I/O
O
26
32
29
26
P4.5
I/O
O
27
33
30
27
P4.4
I/O
O
28 34
28
NC
29 35 31 29 POL
I
30
36
32
30
P0.7
I/O
I/O
31
37
33
31
P0.6
I/O
I/O
32
38
34
32
P0.5
I/O
I/O
33
39
35
33
P0.4
I/O
I/O
34
40
36
34
P0.3
I/O
I/O
35
41
37
35
P0.2
I/O
I/O
36
42
38
36
P0.1
I/O
I/O
37
43
39
37
P0.0
I/O
I/O
38 44 40 38 VDD
I
39 1
39
NC
40 2
1
40
P1.0
I/O
I/O
41 3
2
41
P1.1
I/O
I
42 4
3 42 P1.2 I/O
43 5
4 43 P1.3 I/O
44 6
5 44 P1.4 I/O
Description
P2.3: I/O Port 2 bit 3.
A11: External memory interface Address bit 11.
P2.4: I/O Port 2 bit 5.
A12: External memory interface Address bit 12.
P2.5: I/O Port 2 bit 5.
A13: External memory interface Address bit 13.
P2.6: I/O Port 2 bit 6.
A14: External memory interface Address bit 14.
P2.7: I/O Port 2 bit 7.
A15: External memory interface Address bit 15.
P4.5: I/O Port 4 bit 5.
PSEN: External memory interface Program Store Enable (active-low).
P4.4: I/O Port 4 bit 4.
ALE: External memory interface Address Latch Enable.
Not internally connected
POL: Reset polarity (See “External Reset” on page 33.)
P0.7: I/O Port 0 bit 7.
AD7: External memory interface Address/Data bit 7.
P0.6: I/O Port 0 bit 6.
AD6: External memory interface Address/Data bit 6.
P0.5: I/O Port 0 bit 5.
AD5: External memory interface Address/Data bit 5.
P0.4: I/O Port 0 bit 4.
AD4: External memory interface Address/Data bit 4.
P0.3: I/O Port 0 bit 3.
AD3: External memory interface Address/Data bit 3.
P0.2: I/O Port 0 bit 2.
AD2: External memory interface Address/Data bit 2.
P0.1: I/O Port 0 bit 1.
AD1: External memory interface Address/Data bit 1.
P0.0: I/O Port 0 bit 0.
AD0: External memory interface Address/Data bit 0.
Supply Voltage
Not internally connected
P1.0: I/O Port 1 bit 0.
T2: Timer 2 External Input or Clock Output.
P1.1: I/O Port 1 bit 1.
T2EX: Timer 2 External Capture/Reload Input.
P1.2: I/O Port 1 bit 2.
P1.3: I/O Port 1 bit 3.
P1.4: I/O Port 1 bit 4.
3709D–MICRO–12/11
5

5 Page

AT89LP52 arduino
AT89LP51/52
Table 2-3. Compatibility Mode versus Fast Mode Summary
Feature
Compatibility
Pin Sampling Rate (INT0, INT1, T0, T1, T2, T2EX)
Prescaler Rate
Minimum RST input pulse in System Clocks
12
WDIDLE and DISRTO bit locations
AUXR
Fast
System Clock
2
WDTCON
3. Memory Organization
The AT89LP51/52 uses a Harvard Architecture with separate address spaces for program and
data memory. The program memory has a regular linear address space with support for 64K
bytes of directly addressable application code. The data memory has 256 bytes of internal RAM
and 128 bytes of Special Function Register I/O space. The AT89LP51/52 supports up to 64K
bytes of external data memory, with portions of the external data memory space implemented on
chip as nonvolatile Flash data memory. External program memory is supported for addresses
above 8K. The memory address spaces of the AT89LP51/52 are listed in Table 3-1.
Table 3-1. AT89LP51/52 Memory Address Spaces
Name
Description
Range
DATA
Directly addressable internal RAM
00H–7FH
IDATA
Indirectly addressable internal RAM and stack space
00H–FFH
SFR
Directly addressable I/O register space
80H–FFH
FDATA
On-chip nonvolatile Flash data memory
0000H–00FFH
XDATA
External data memory
0100H–FFFFH
CODE
On-chip nonvolatile Flash program memory
0000H–0FFFH (AT89LP51)
0000H–1FFFH (AT89LP52)
XCODE
External program memory
2000H–FFFFH (AT89LP51)
1000H–FFFFH (AT89LP52)
SIG On-chip nonvolatile Flash signature array
0000H–01FFH
3.1 Program Memory
The AT89LP51/52 contains 4K/8K bytes of on-chip In-System Programmable Flash memory for
program storage, plus support for up to 60K/56K bytes of external program memory. The Flash
memory has an endurance of at least 10,000 write/erase cycles and a minimum data retention
time of 10 years. The reset and interrupt vectors are located within the first 83 bytes of program
memory (refer to Table 9-1 on page 38). Constant tables can be allocated within the entire 64K
program memory address space for access by the MOVC instruction. A map of the
AT89LP51/52 program memory is shown in Figure 3-1.
3709D–MICRO–12/11
11

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