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PDF AT89LP3240 Datasheet ( Hoja de datos )

Número de pieza AT89LP3240
Descripción 8-bit Microcontroller
Fabricantes ATMEL 
Logotipo ATMEL Logotipo
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AT89LP3240 datasheet

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AT89LP3240 pdf
AT89LP3240/6440
Table 1-1. AT89LP3240/6440 Pin Description
Pin Number
TQFP PLCC PDIP VQFN Symbol Type
17 23 20 17 GND
I
I/O
18 24 21 18 P2.0 I/O
O
I/O
19 25 22 19 P2.1 I/O
O
I/O
20
26
23
20
P2.1
I/O
O
O
I/O
21
27
24
21
P2.3
I/O
O
O
I/O
22 28 25 22 P2.4
I
O
I/O
23 29 26 23 P2.5
I
O
I/O
24 30 27 24 P2.6
I
O
I/O
25 31 28 25 P2.7
I
O
26 32 29 26 P4.5 I/O
27
33
30
27
P4.4
I/O
O
28 34
28 GND
I
I/O
29 35 31 29 P4.3 I/O
I/O
30 36 32 30 P0.7
O
I
I/O
31 37 33 31 P0.6
O
I
I/O
32 38 34 32 P0.5
O
I
I/O
33 39 35 33 P0.4
O
I
I/O
34 40 36 34 P0.3
O
I
Description
Ground
P2.0: User-configurable I/O Port 2 bit 0.
CCA: Timer 2 Channel A Compare Output or Capture Input.
A8: External memory interface Address bit 8.
P2.1: User-configurable I/O Port 2 bit 1.
CCB: Timer 2 Channel B Compare Output or Capture Input.
A9: External memory interface Address bit 9.
P2.2: User-configurable I/O Port 2 bit 2.
CCC: Timer 2 Channel C Compare Output or Capture Input.
A10: External memory interface Address bit 10.
DA-: DAC negative differential output.
P2.3: User-configurable I/O Port 2 bit 3.
CCD: Timer 2 Channel D Compare Output or Capture Input.
A11: External memory interface Address bit 11.
D+-: DAC positive differential output.
P2.4: User-configurable I/O Port 2 bit 5.
AIN0: Analog Comparator Input 0.
A12: External memory interface Address bit 12.
P2.5: User-configurable I/O Port 2 bit 5.
AIN1: Analog Comparator Input 1.
A13: External memory interface Address bit 13.
P2.6: User-configurable I/O Port 2 bit 6.
AIN2: Analog Comparator Input 2.
A14: External memory interface Address bit 14.
P2.7: User-configurable I/O Port 2 bit 7.
AIN3: Analog Comparator Input 3.
A15: External memory interface Address bit 15.
P4.5: User-configurable I/O Port 4 bit 5.
P4.4: User-configurable I/O Port 4 bit 4.
ALE: External memory interface Address Latch Enable.
Ground
P4.3: User-configurable I/O Port 4 bit 3.
DDA: Serial Data input/output for On-Chip Debug Interface when OCD is enabled and
the Crystal oscillator is selected as the clock source.
P0.7: User-configurable I/O Port 0 bit 7.
AD7: External memory interface Address/Data bit 7.
ADC7: ADC analog input 7.
P0.6: User-configurable I/O Port 0 bit 6.
AD6: External memory interface Address/Data bit 6.
ADC6: ADC analog input 6.
P0.5: User-configurable I/O Port 0 bit 5.
AD5: External memory interface Address/Data bit 5.
ADC5: ADC analog input 5.
P0.4: User-configurable I/O Port 0 bit 4.
AD4: External memory interface Address/Data bit 4.
ADC4: ADC analog input 4.
P0.3: User-configurable I/O Port 0 bit 3.
AD3: External memory interface Address/Data bit 3.
ADC3: ADC analog input 3.
3706C–MICRO–2/11
5

5 Page

AT89LP3240 arduino
There is no difference in counting rate between Timer 2’s Auto-Reload/Capture and Baud
Rate/Clock Out modes. All modes increment the timer once per clock cycle. Timer 2 in Auto-
Reload/Capture mode increments at 12 times the rate of standard 8051s. Setting TPS3-0 =
1101B will force Timer 2 to count every twelve clocks. Timer 2 in Baud Rate or Clock Out mode
increments at twice the rate of standard 8051s. Setting TPS3-0 = 0001B will force Timer 2 to
count every two clocks.
2.3.6
Serial Port
The baud rate of the UART in Mode 0 defaults to 1/4 the clock frequency, compared to 1/12 the
clock frequency in the standard 8051. In should also be noted that when using Timer 1 to gener-
ate the baud rate in UART Modes 1 or 3, the timer counts at the clock frequency and not at 1/12
the clock frequency. To maintain the same baud rate in the AT89LP3240/6440 while running at
the same frequency as a standard 8051, the time-out period must be 12 times longer. Mode 1 of
Timer 1 supports 16-bit auto-reload to facilitate longer time-out periods for generating low baud
rates.
Timer 2 generated baud rates are twice as fast in the AT89LP3240/6440 than on standard
8051s when operating at the same frequency. The Timer Prescaler can also scale the baud rate
to match an existing application.
2.3.7 SPI
The Serial Peripheral Interface (SPI) has a dedicated interrupt vector. The ESPI (IE2.2) bit
replaces SPIE (SPCR.7). SPCR.7 (TSCK) now enables timer-generated baud rate.
The SPI includes Mode Fault detection. If multiple-master capabilities are not required, SSIG
(SPSR.2) must be set to one for master mode to function correctly when SS (P1.4) is a general
purpose I/O.
2.3.8
Watchdog Timer
The Watchdog Timer in AT89LP3240/6440 counts at a rate of once per clock cycle. This com-
pares to once every 12 clocks in the standard 8051. A common prescaler is available to divide
the time base for all timers and reduce the counting rate.
2.3.9 I/O Ports
The I/O ports of the AT89LP3240/6440 may be configured in four different modes. By default all
the I/O ports revert to input-only (tristated) mode at power-up or reset. In the standard 8051, all
ports are weakly pulled high during power-up or reset. To enable 8051-like ports, the ports must
be put into quasi-bidirectional mode by clearing the P1M0, P2M0, P3M0 and P4M0 SFRs. The
user can also configure the ports to start in quasi-bidirectional mode by disabling the Tristate-
Port User Fuse. When this fuse is disabled, P1M0, P2M0, P3M0 and P4M0 will reset to 00h
instead of FFh and the ports will be weakly pulled high. Port 0 and the upper nibble of Port 2
always power up tristated regardless of the fuse setting due to their analog functions.
2.3.10
External Memory Interface
The AT89LP3240/6440 does not support external program memory. The PSEN and EA func-
tions are not supported and those pins are replaced with general purpose I/O. The ALE strobe
does not toggle continuously and cannot be used as a board-level clock.
10 AT89LP3240/6440
3706C–MICRO–2/11

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