DataSheet.es AT89LP51IC2 Hoja de datos PDF



PDF AT89LP51IC2 Datasheet ( Hoja de datos )

Número de pieza AT89LP51IC2
Descripción 8-bit Flash Microcontroller
Fabricantes ATMEL 
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AT89LP51IC2 datasheet

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AT89LP51IC2 pdf
AT89LP51RB2/RC2/IC2 Preliminary
Table 1-1. Atmel AT89LP51RB2/RC2/IC2 Pin Description
Pin Number
VQFP
VQFN PLCC
(1)
PDIP
Symbol
Type Description
16 22 20 GND
I Ground
17 23
P4.3
I/O P4.3: User-configurable I/O Port 4bit 3.
I/O DDA: Bidirectional Debug Data line for the On-Chip Debug Interface when OCD is enabled.
18
24
21
P2.0
I/O P2.0: User-configurable I/O Port 2 bit 0.
O A8: External memory interface Address bit 8.
19
25
22
P2.1
I/O P2.1: User-configurable I/O Port 2 bit 1.
O A9: External memory interface Address bit 9.
I/O P2.2: User-configurable I/O Port 2 bit 2.
20 26 23
P2.1
O DA-: DAC negative differential output.
O A10: External memory interface Address bit 10.
I/O P2.3: User-configurable I/O Port 2 bit 3.
21 27 24
P2.3
O DA+-: DAC positive differential output.
O A11: External memory interface Address bit 11.
I/O P2.4: User-configurable I/O Port 2 bit 5.
22 28 25 P2.4
I AIN0: Analog Comparator Input 0.
O A12: External memory interface Address bit 12.
I/O P2.5: User-configurable I/O Port 2 bit 5.
23 29 26 P2.5
I AIN1: Analog Comparator Input 1.
O A13: External memory interface Address bit 13.
I/O P2.6: User-configurable I/O Port 2 bit 6.
24 30 27 P2.6
I AIN2: Analog Comparator Input 2.
O A14: External memory interface Address bit 14.
I/O P2.7: User-configurable I/O Port 2 bit 7.
25 31 28 P2.7
I AIN3: Analog Comparator Input 3.
O A15: External memory interface Address bit 15.
26
32
29
P4.5
I/O P4.5: User-configurable I/O Port 4 bit 5.
O PSEN: External memory interface Program Store Enable (active-low).
27
33
30
P4.4
I/O P4.4: User-configurable I/O Port 4 bit 4.
I/O ALE: External memory interface Address Latch Enable.
28 34
P4.0
I/O
P4.0: User-configurable I/O Port 4 bit 0.
SCL: TWI Serial Clock line. This line is an output in mater mode and an input in slave mode.
29 35 31 POL
I POL: Reset polarity (See “External Reset” on page 53.)
30
36
32
P0.7
I/O P0.7: User-configurable I/O Port 0 bit 7.
I/O AD7: External memory interface Address/Data bit 7.
I/O P0.6: User-configurable I/O Port 0 bit 6.
31 37 33 P0.6 I/O AD6: External memory interface Address/Data bit 6.
I ADC6: ADC analog input 6.
I/O P0.5: User-configurable I/O Port 0 bit 5.
32 38 34 P0.5 I/O AD5: External memory interface Address/Data bit 5.
I ADC5: ADC analog input 5.
I/O P0.4: User-configurable I/O Port 0 bit 4.
33 39 35 P0.4 I/O AD4: External memory interface Address/Data bit 4.
I ADC4: ADC analog input 4.
I/O P0.3: User-configurable I/O Port 0 bit 3.
34 40 36 P0.3 I/O AD3: External memory interface Address/Data bit 3.
I ADC3: ADC analog input 3.
3722A–MICRO–10/11
5

5 Page

AT89LP51IC2 arduino
2.3 Comparison to the Atmel AT89C51RB2/RC2/IC2
The Atmel® AT89LP51RB2/RC2/IC2 is part of a family of devices with enhanced features that
are fully binary compatible with the 8051 instruction set. The AT89LP51RB2/RC2/IC2 has two
modes of operations, Compatibility mode and Fast mode. In Compatibility mode the instruction
timing, peripheral behavior, SFR addresses, bit assignments and pin functions are identical to
the existing Atmel AT89C51RB2/RC2/IC2 product. Additional enhancements are transparent to
the user and can be used if desired. Fast mode allows greater performance, but with some dif-
ferences in behavior. The major enhancements from the AT89C51RB2/RC2/IC2 are outlined in
the following paragraphs and may be useful to users migrating to the AT89LP51RB2/RC2/IC2
from older devices. A summary of the differences between Compatibility and Fast modes is
given in Table 2-3 on page 12. See also the Application note “Migrating from
AT89C51RB2/RC2/IC2 to AT89LP51RB2/RC2/IC2.”
2.3.1
Instruction Execution
In Compatibility mode the Atmel® AT89LP51RB2/RC2/IC2 CPU uses the six-state machine
cycle of the standard 8051 where instruction bytes are fetched every three system clock cycles.
Execution times in this mode are identical to the Atmel AT89C51RB2/RC2/IC2. For greater per-
formance the user can enable Fast mode by disabling the Compatibility fuse. In Fast mode the
CPU fetches one code byte from memory every clock cycle instead of every three clock cycles.
This greatly increases the throughput of the CPU. Each standard instruction executes in only
one to four clock cycles. See “Instruction Set Summary” on page 173 for more details. Any soft-
ware delay loops or instruction-based timing operations may need to be retuned to achieve the
desired results in Fast mode.
2.3.2
System Clock
The system clock source is not limited to a crystal or external clock. The system clock source is
selectable between the crystal oscillator, an externally driven clock and an internal 8.0MHz RC
oscillator for AT89LP51RB2/RC2 and clock source A of AT89LP51IC2. Clock source B of
AT89LP51IC2 is not limited to a 32 kHz crystal. The clock source B is selectable between the 32
kHz crystal oscillator, an externally driven clock and an internal 8.0MHz RC oscillator. Unlike
AT89C51IC2, the X2 and CKRL features will also affect the OSCB source.
By default in Compatibility mode the system clock frequency is divided by 2 from the externally
supplied XTAL1 frequency for compatibility with standard 8051s (12 clocks per machine cycle).
The System Clock Divider can scale the system clock versus the oscillator source (See Section
6.8 on page 47). The divide-by-2 can be disabled to operate in X2 mode (6 clocks per machine
cycle) or the clock may be further divided to reduce the operating frequency. In Fast mode the
clock divider defaults to divide by 1.
2.3.3 Reset
The RST pin of the AT89LP51RB2/RC2/IC2 has selectable polarity using the POL pin (formerly
EA). When POL is high the RST pin is active high with a pull-down resistor and when POL is low
the RST pin is active low with a pull-up resistor. For existing AT89C51RB2/RC2/IC2 sockets
where EA is tied to VDD, replacing AT89C51RB2/RC2/IC2 with AT89LP51RB2/RC2/IC2 will
maintain the active high reset. Note that forcing external execution by tying EA low is not
supported.
The AT89LP51RB2/RC2/IC2 includes an on-chip Power-On Reset and Brown-out Detector cir-
cuit that ensures that the device is reset from system power up. In most cases a RC startup
10 AT89LP51RB2/RC2/IC2 Preliminary
3722A–MICRO–10/11

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