PDF AT89LP51RC2 Datasheet ( Hoja de datos )

Número de pieza AT89LP51RC2
Descripción 8-bit Flash Microcontroller
Fabricantes ATMEL 
Logotipo ATMEL Logotipo

Total 30 Páginas
AT89LP51RC2 Hoja de datos, Descripción, Manual
8-bit Microcontroller Compatible with 8051 Products
Enhanced 8051 Architecture
– Single Clock Cycle per Byte Fetch
– 12 Clock per Machine Cycle Compatibility Mode
– Up to 20 MIPS Throughput at 20 MHz Clock Frequency
– Fully Static Operation: 0 Hz to 20 MHz
– On-chip 2-cycle Hardware Multiplier
– 16x16 Multiply–Accumulate Unit
– 256 x 8 Internal RAM
– On-chip 1152 Bytes Expanded RAM (ERAM)
• Software Selectable Size (0, 256, 512, 768, 1024 or 1152 Bytes)
– Dual Data Pointers
– 4-level Interrupt Priority
Nonvolatile Program and Data Memory
– 24KB/32KB of In-System Programmable (ISP) Flash Program Memory
– 512-byte User Signature Array
– Endurance: 10,000 Write/Erase Cycles
– Serial Interface for Program Downloading
– 2KB Boot ROM Contains Low Level Flash Programming Routines and a Default
Serial Bootloader
Peripheral Features
– Three 16-bit Enhanced Timer/Counters
– Seven 8-bit PWM Outputs
– 16-bit Programmable Counter Array
• High Speed Output, Compare/Capture
• Pulse Width Modulation, Watchdog Timer Capabilities
– Enhanced UART with Automatic Address Recognition and Framing
Error Detection
– Enhanced Master/Slave SPI with Double-buffered Send/Receive
Two Wire Interface 400K bit/s
– Programmable Watchdog Timer with Software Reset
– 8 General-purpose Interrupt and Keyboard Interface Pins
Special Microcontroller Features
– Dual Oscillator Support: Crystal, 32 kHz Crystal, 8 MHz Internal (AT89LP51IC2)
– Two-wire On-Chip Debug Interface
– Brown-out Detection and Power-on Reset with Power-off Flag
– Selectable Polarity External Reset Pin
– Low Power Idle and Power-down Modes
– Interrupt Recovery from Power-down Mode
– 8-bit Clock Prescaler
I/O and Packages
– Up to 40 Programmable I/O Lines
– Green (Pb/Halide-free) PLCC44, VQFP44, QFN44. PDIP40
– Configurable I/O Modes
• Quasi-bidirectional (80C51 Style), Input-only (Tristate)
• Push-pull CMOS Output, Open-drain
Operating Conditions
– 2.4V to 5.5V VCC Voltage Range
– -40° C to 85°C Temperature Range
– 0 to 20 MHz @ 2.4V–5.5V (Single-cycle)
8-bit Flash
with 24K/32K
bytes Program

1 page

AT89LP51RC2 pdf
AT89LP51RB2/RC2/IC2 Preliminary
Table 1-1. Atmel AT89LP51RB2/RC2/IC2 Pin Description
Pin Number
Type Description
16 22 20 GND
I Ground
17 23
I/O P4.3: User-configurable I/O Port 4bit 3.
I/O DDA: Bidirectional Debug Data line for the On-Chip Debug Interface when OCD is enabled.
I/O P2.0: User-configurable I/O Port 2 bit 0.
O A8: External memory interface Address bit 8.
I/O P2.1: User-configurable I/O Port 2 bit 1.
O A9: External memory interface Address bit 9.
I/O P2.2: User-configurable I/O Port 2 bit 2.
20 26 23
O DA-: DAC negative differential output.
O A10: External memory interface Address bit 10.
I/O P2.3: User-configurable I/O Port 2 bit 3.
21 27 24
O DA+-: DAC positive differential output.
O A11: External memory interface Address bit 11.
I/O P2.4: User-configurable I/O Port 2 bit 5.
22 28 25 P2.4
I AIN0: Analog Comparator Input 0.
O A12: External memory interface Address bit 12.
I/O P2.5: User-configurable I/O Port 2 bit 5.
23 29 26 P2.5
I AIN1: Analog Comparator Input 1.
O A13: External memory interface Address bit 13.
I/O P2.6: User-configurable I/O Port 2 bit 6.
24 30 27 P2.6
I AIN2: Analog Comparator Input 2.
O A14: External memory interface Address bit 14.
I/O P2.7: User-configurable I/O Port 2 bit 7.
25 31 28 P2.7
I AIN3: Analog Comparator Input 3.
O A15: External memory interface Address bit 15.
I/O P4.5: User-configurable I/O Port 4 bit 5.
O PSEN: External memory interface Program Store Enable (active-low).
I/O P4.4: User-configurable I/O Port 4 bit 4.
I/O ALE: External memory interface Address Latch Enable.
28 34
P4.0: User-configurable I/O Port 4 bit 0.
SCL: TWI Serial Clock line. This line is an output in mater mode and an input in slave mode.
29 35 31 POL
I POL: Reset polarity (See “External Reset” on page 53.)
I/O P0.7: User-configurable I/O Port 0 bit 7.
I/O AD7: External memory interface Address/Data bit 7.
I/O P0.6: User-configurable I/O Port 0 bit 6.
31 37 33 P0.6 I/O AD6: External memory interface Address/Data bit 6.
I ADC6: ADC analog input 6.
I/O P0.5: User-configurable I/O Port 0 bit 5.
32 38 34 P0.5 I/O AD5: External memory interface Address/Data bit 5.
I ADC5: ADC analog input 5.
I/O P0.4: User-configurable I/O Port 0 bit 4.
33 39 35 P0.4 I/O AD4: External memory interface Address/Data bit 4.
I ADC4: ADC analog input 4.
I/O P0.3: User-configurable I/O Port 0 bit 3.
34 40 36 P0.3 I/O AD3: External memory interface Address/Data bit 3.
I ADC3: ADC analog input 3.

5 Page

AT89LP51RC2 arduino
AT89LP51RB2/RC2/IC2 Preliminary
circuit is not required on the RST pin, reducing system cost, and the RST pin may be left uncon-
nected if a board-level reset is not present.
A common prescaler is available to divide the time base for Timer 0, Timer 1, Timer 2 and the
WDT. The TPS3-0 bits in the CLKREG SFR control the prescaler (Table 6-8 on page 47). In
Compatibility mode TPS3-0 defaults to 0101B, which causes the timers to count once every
machine cycle. The counting rate can be adjusted linearly from the system clock rate to 1/16 of
the system clock rate by changing TPS3-0. In Fast mode TPS3-0 defaults to 0000B, or the system
clock rate. TPS does not affect Timer 2 in Clock Out or Baud Generator modes.
In Compatibility mode the sampling of the external Timer/Counter pins: T0, T1, T2 and T2EX;
and the external interrupt pins, INT0 and INT1, is also controlled by the prescaler. In Fast mode
these pins are always sampled at the system clock rate.
Both Timer 0 and Timer 1 can toggle their respective counter pins, T0 and T1, when they over-
flow by setting the output enable bits in TCONB.
Interrupt Handling
Fast mode allows for faster interrupt response due to the shorter instruction execution times.
Keyboard Interface
The AT89LP51RB2/RC2/IC2 does not clear the keyboard flag register (KBF) after a read. Each
bit must be cleared in software. This allows the interrupt to be generate once per flag when mul-
tiple flags are set, if desired. To mimic the old behavior the service routine must clear the whole
The keyboard can also support general edge-triggered interrupts with the addition of the
KBMOD register.
Serial Port
The timer prescaler increases the range of achievable baud rates when using Timer 1 to gener-
ate the baud rate in UART Modes 1 or 3, including an increase in the maximum baud rate
available in Compatibility mode. Additional features include automatic address recognition and
framing error detection.
The shift register mode (Mode 0) has been enhanced with more control of the polarity, phase
and frequency of the clock and full-duplex operation. This allows emulation of master serial
peripheral (SPI) and two-wire (TWI) interfaces.
I/O Ports
The P0, P1, P2 and P3 I/O ports of the AT89LP51RB2/RC2/IC2 may be configured in four differ-
ent modes. The default setting depends on the Tristate-Port User Fuse. When the fuse is set all
the I/O ports revert to input-only (tristated) mode at power-up or reset. When the fuse is not
active, ports P1, P2 and P3 start in quasi-bidirectional mode and P0 starts in open-drain mode.
P4 always operates in quasi-bidirectional mode. P0 can be configured to have internal pull-ups
by placing it in quasi-bidirectional or output modes. This can reduce system cost by removing
the need for external pull-ups on Port 0.
The P4.4–P4.7 pins are additional I/Os that replace the normally dedicated ALE, PSEN, XTAL1
and XTAL2 pins of the AT89C51RB2/RC2/IC2. These pins can be used as additional I/Os
depending on the configuration of the clock and external memory.

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