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PDF IN93AA66D Data sheet ( Hoja de datos )

Número de pieza IN93AA66D
Descripción 4K-BIT SERIAL EEPROM
Fabricantes Integral 
Logotipo Integral Logotipo



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No Preview Available ! IN93AA66D Hoja de datos, Descripción, Manual

IN93AA66N, IN93AA66D
4K-BIT SERIAL EEPROM WITH MICROWIRE INTEFACE
(compatible to САТ93С66 Catalyst)
DESCRIPTION
The IN93LC66 is a Electric erasable programmable ROM (EEPROM) memory data capac-
ity 4K (512x8 or 256x16) with 3-wire interface.
There are 3 modification of ICs
A: ICs IN93AA66AD/AN are 8 bits registers (512х8) - ORG pin not used
B: ICs IN93AA66BD/BN are 16 bits registers (256х16) - ORG pin not used
C: ICs IN93AA66CN/CD are configured as either registers of 8 bits (ORG pin at GND) or
16 bits (ORG pin at VCC, or not connected). Each register can be written (or read) serially
by using the DI (or DO) pin.
The ICs is purposed for reading, writing & nonvolatile data storage. ICs can be used in
TV-sets, telecom equipment & consumer electronic devices.
FEATURES
100 year data (4K) retention for Ta=25oC;
Single power supply source (VСС = 1,8 V – 6,0 V);
Build-in voltage multiplier;
Serial I/O bus;
Autoincrement of address word;
Self-timed write cycle;
1,000,000 Program/erase cycles;
Power-up internal logic setup;
Read cycles quantity are not limited;
Low power consumption;
Operating temperature range -40 … +85 oC.
N SUFFIX
DIP
8
1 D SUFFIX
8 SOIC
1
PIN FUNCTIONS
Pin
Name
Function
CS Chip Select
CS 01
08 Vcc
SK Clock Input
DI Serial Data Input
SK 02
07 NC
DO
VCC
GND
ORG*
Serial Data Output
+1.8 to 6.0V Power Supply
Ground
Memory Organization pin *
DI 03
DO 04
06 ORG*(NC)
05 GND
NC No Connection
Note
* this pin is present only in IN93AA66CN, IN93AA66CD:
When the ORG pin is connected to VCC, the x16 organization is selected.
When it is connected to ground, the x8 pin is selected.
If the ORG pin is left unconnected, then an internal pullup device will select the x16 organization.
Ver.00/13.10.2008
1 IN93AA66-TSe.doc
886784

1 page




IN93AA66D pdf
Instruction Set
Start
Instruction Bit
READ
1
ERASE
1
WRITE
1
EWEN
EWDS
ERAL
1
1
1
WRAL
1
Op-
code
10
11
01
00
00
00
00
IN93AA66N, IN93AA66D
Address
x8
x16
A8-A0
A7-A0
A8-A0
A7-A0
A8-A0
11XXXXXXX
00XXXXXXX
10XXXXXXX
A7-A0
11XXXXXX
00XXXXXX
10XXXXXX
01XXXXXXX
01XXXXXX
Data
x8 x16
D7-D0 D15-D0
D7-D0 D15-D0
Comments
Read Address
AN- АО
Clear Address
AN- АО
Write Address
AN- АО
Write Enable
Write Disable
Clear All
Addresses
Write All
Addresses
There are 7 instructions 11bit for 128х16 or 12bit for 256x8 memory organization to execute
WRITE, ERASE or READ operation
The format for all instructions sent to the device is a logical "1" start bit, a 2-bits (or 4-bits) opera-
tion code, 8-bit address (256х16)/ 9-bit address (512x8).
A 16-bit data field (organization 256х16) or 8-bit data field (organization 512x8) is addition-
ally required for write operations.
Read Instruction Timing
EWEN/EWDS Instruction Timing
The IN93AA66 powers up switch IC to the write disable state. Any writing after power-up
Ver.00/13.10.2008
5 IN93AA66-TSe.doc
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