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PDF SAM9N12 Data sheet ( Hoja de datos )

Número de pieza SAM9N12
Descripción SMART ARM-based Embedded MPU
Fabricantes ATMEL Corporation 
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SAM9N12/SAM9CN11/SAM9CN12
Atmel | SMART ARM-based Embedded MPU
DATASHEET
Description
The Atmel® | SMART SAM9N and SAM9CN ARM926EJ-S™-based embedded
MPUs offer the frequently-requested combination of user interface functionality
and high data rate connectivity, with LCD controller, resistive touchscreen,
multiple UARTs, SPI, I2C, full-speed USB Host and Device and SDIO.
These eMPUs support the latest generation of LPDDR/DDR2 and NAND Flash
memory interfaces for program and data storage. An internal 133 MHz multi-layer
bus architecture associated with eight DMA channels and distributed memory—
including a 32-Kbyte SRAM—sustains the high bandwidth required by the
processor and the high-speed peripherals.
The SAM9CN devices offer on-chip hardware accelerators with DMA support that
enable high-speed data encryption and authentication of transferred data or
applications. Supported standards are up to 256-bit AES, and FIPS Publication
180-2 compliant SHA1 and SHA256. A True Random Number Generator is
embedded for key generation and exchange protocols. The devices also feature
fuse bits for crypto key (SAM9CN12), user configuration (SAM9N12 and
SAM9CN11) and device configuration (all). The SAM9CN12 includes a secure
Boot ROM; the SAM9N12 and SAM9CN11 include a standard Boot ROM.
The I/Os support 1.8V or 3.3V operation and are independently configurable for
the memory interface and peripheral I/Os. This feature eliminates the need for any
external level shifters, while 0.8mm ball pitch packages lower PCB cost and
complexity.
The SAM9N and SAM9CN power management controllers feature efficient clock
gating and a battery backup section that minimizes power consumption in active
and standby modes. The following table presents the embedded features of each
device.
Device Configuration
Feature
Standard Boot with BSC
Secure Boot
TRNG
AES
SHA
SAM9N12
SAM9CN11
SAM9CN12
Atmel-11063L-ATARM-SAM9N12-SAM9CN11-SAM9CN12-Datasheet_28-Oct-15

1 page




SAM9N12 pdf
2. Signal Description
Table 2-1 gives details on the signal names classified by peripheral.
Table 2-1. Signal Description List
Signal Name
Function
Clocks, Oscillators and PLLs
XIN Main Oscillator Input
XOUT
Main Oscillator Output
XIN32
Slow Clock Oscillator Input
XOUT32
Slow Clock Oscillator Output
PCK0–PCK1
Programmable Clock Output
Shutdown, Wakeup Logic
SHDN
Shut-Down Control
WKUP
Wake-Up Input
ICE and JTAG
TCK
Test Clock
TDI Test Data In
TDO
Test Data Out
TMS
Test Mode Select
JTAGSEL
JTAG Selection
RTCK
Return Test Clock
Reset/Test
NRST
Microcontroller Reset
NTRST
Test Reset Signal
BMS
Boot Mode Select
Debug Unit - DBGU
DRXD
Debug Receive Data
DTXD
Debug Transmit Data
Advanced Interrupt Controller - AIC
IRQ External Interrupt Input
FIQ Fast Interrupt Input
PIO Controller - PIOA / PIOB / PIOC / PIOD
PA0–PA31
Parallel IO Controller A
PB0–PB18
Parallel IO Controller B
PC0–PC31
Parallel IO Controller C
PD0–PD21
Parallel IO Controller D
Type
Active Level
Input
Output
Input
Output
Output
Output
Input
Input
Input
Output
Input
Input
Output
I/O
Input
Input
Low
Input
Output
Input
Input
I/O
I/O
I/O
I/O
SAM9N12-SAM9CN11-SAM9CN12 [DATASHEET]
Atmel-11063L-ATARM-SAM9N12-SAM9CN11-SAM9CN12-Datasheet_28-Oct-15
5

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SAM9N12 arduino
3.3 217-ball BGA Package Pinout
Table 3-1.
BGA217 Pin Description
Primary
Ball Power Rail I/O Type
T3 VDDIOP0
GPIO
U2 VDDIOP0
GPIO
U3 VDDIOP0
GPIO
P4 VDDIOP0
GPIO
T4 VDDIOP0
GPIO
U4 VDDIOP0
GPIO
P5 VDDIOP0
GPIO
R4 VDDIOP0
GPIO
U6 VDDIOP0
GPIO
R5 VDDIOP0
GPIO
R6 VDDIOP0
GPIO
T5 VDDIOP0
GPIO
T6 VDDIOP0
GPIO
U5 VDDIOP0 GPIO_CLK
U7 VDDIOP0
GPIO
T7 VDDIOP0
GPIO
R7 VDDIOP0
GPIO
U8 VDDIOP0 GPIO_CLK
P8 VDDIOP0
GPIO
T8 VDDIOP0
GPIO
R8 VDDIOP0
GPIO
U9 VDDIOP0
GPIO
U10 VDDIOP0
GPIO
T9 VDDIOP0 GPIO_CLK
U11 VDDIOP0
GPIO
T10 VDDIOP0
GPIO
R9 VDDIOP0
GPIO
U12 VDDIOP0
GPIO
T11 VDDIOP0
GPIO
U13 VDDIOP0
GPIO
R10 VDDIOP0
GPIO
T12 VDDIOP0
GPIO
E4 VDDANA
GPIO
F3 VDDANA
GPIO
F4 VDDANA
GPIO
F2 VDDANA
GPIO
G4 VDDANA GPIO_CLK
G3 VDDANA
GPIO
Signal
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PA8
PA9
PA10
PA11
PA12
PA13
PA14
PA15
PA16
PA17
PA18
PA19
PA20
PA21
PA22
PA23
PA24
PA25
PA26
PA27
PA28
PA29
PA30
PA31
PB0
PB1
PB2
PB3
PB4
PB5
Dir
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Alternate
Signal Dir
PIO Peripheral A
Signal
TXD0
RXD0
RTS0
CTS0
SCK0
TXD1
RXD1
TXD2
RXD2
DRXD
DTXD
SPI0_MISO
SPI0_MOSI
SPI0_SPCK
SPI0_NPCS0
MCDA0
MCCDA
MCCK
MCDA1
MCDA2
MCDA3
TIOA0
TIOA1
TIOA2
TCLK0
TCLK1
TCLK2
TIOB0
TIOB1
TIOB2
TWD0
TWCK0
Dir
O
I
O
I
I/O
O
I
O
I
I
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I/O
I/O
I/O
I/O
O
PIO Peripheral B
Signal
SPI1_NPCS1
SPI0_NPCS2
Dir
O
O
SPI0_NPCS1
SPI1_NPCS0
O
I/O
MCDA4
MCDA5
MCDA6
MCDA7
I/O
I/O
I/O
I/O
SPI1_MISO
SPI1_MOSI
SPI1_SPCK
TK
TF
TD
RD
RK
RF
SPI1_NPCS3
SPI1_NPCS2
RTS2
CTS2
SCK2
SPI0_NPCS3
I/O
I/O
I/O
I/O
I/O
O
I
I/O
I/O
O
O
O
I
I/O
O
PIO Peripheral C
Signal
Dir
Reset State
Signal, Dir,
PU, PD, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
SAM9N12-SAM9CN11-SAM9CN12 [DATASHEET]
Atmel-11063L-ATARM-SAM9N12-SAM9CN11-SAM9CN12-Datasheet_28-Oct-15
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