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PDF OTM8009A Data sheet ( Hoja de datos )

Número de pieza OTM8009A
Descripción 1440-channel 8-bit Source Driver and 864 Gate Driver
Fabricantes ORISE　
Logotipo ORISE Logotipo



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OTM8009A
1440-channel 8-bit Source Driver and
864 Gate Driver with System-on-chip
for Color Amorphous TFT-LCDs
Preliminary
FEB. 22, 2012
Version 0.8
ORISE Technology reserves the right to change this documentation without prior notice. Information provided by ORISE Technology is believed to be
accurate and reliable. However, ORISE Technology makes no warranty for any errors which may appear in this document. Contact ORISE Technology to
obtain the latest version of device specifications before placing your order. No responsibility is assumed by ORISE Technology for any infringement of patent
or other rights of third parties which may result from its use. In addition, ORISE Technology products are not authorized for use as critical components in life
support devices/ systems or aviation devices/systems, where a malfunction or failure of the product may reasonably be expected to result in significant injury to
the user, without the express written approval of ORISE Technology.

1 page




OTM8009A pdf
Preliminary
OTM8009A
5.3.42. GOACLKB3(CED0h~CED6h) GOA CLKB3 Setting........................................................................................................... 142
5.3.43. GOACLKB4(CED7h~CEDDh) GOA CLKB4 Setting .......................................................................................................... 143
5.3.44. GOACLKC1(CF80h~CF86h) GOA CLKC1 Setting ............................................................................................................ 144
5.3.45. GOACLKC2(CF87h~CF8Dh) GOA CLKC2 Setting ........................................................................................................... 145
5.3.46. GOACLKC3(CF90h~CF96h) GOA CLKC3 Setting ............................................................................................................ 146
5.3.47. GOACLKC4(CF97h~CF9Dh) GOA CLKC4 Setting ........................................................................................................... 147
5.3.48. GOACLKD1(CFA0h~CFA6h) GOA CLKD1 Setting............................................................................................................ 148
5.3.49. GOACLKD2(CFA7h~CFADh) GOA CLKD2 Setting ........................................................................................................... 149
5.3.50. GOACLKD3(CFB0h~CFB6h) GOA CLKD3 Setting ........................................................................................................... 150
5.3.51. GOACLKD4(CFB7h~CFBDh) GOA CLKD4 Setting........................................................................................................... 151
5.3.52. GOAECLK(CFC0h~CFC5h) GOA ECLK Setting ............................................................................................................... 152
5.3.53. GOAOPT1(CFC6h) GOA Other Options 1 ......................................................................................................................... 154
5.3.54. GOATGOPT(CFC7h~CFC9h) GOA Signal Toggle Option Setting..................................................................................... 155
5.3.55. WRID1(D000h) ID1 Setting ................................................................................................................................................ 157
5.3.56. WRID2(D100h) ID2/ID3 Setting ......................................................................................................................................... 157
5.3.57. WRDDB(D200h) DDB Setting ............................................................................................................................................ 158
5.3.58. EXTCCHK (D300h): EXTC Check........................................................................................................................................ 159
5.3.59. CESET1 (D400h): CE Correction Characteristics Setting 1............................................................................................... 160
5.3.60. CESET2(D500h): CE Correction Characteristics Setting 2................................................................................................ 161
5.3.61. CEEN(D680h): CE Enable ................................................................................................................................................. 162
5.3.62. AIEEN(D700h): AIE Enable................................................................................................................................................ 163
5.3.63. GVDDSET (D800h): GVDD/NGVDD .................................................................................................................................... 164
5.3.64. VCOMDC (D900h): VCOM voltage setting............................................................................................................................ 165
5.3.65. GMCT2.2P (E100h): Gamma Correction Characteristics Setting (2.2 + ).......................................................................... 166
5.3.66. GMCT2.2N (E200h): Gamma Correction Characteristics Setting (2.2 - ) ................................................................................ 167
5.3.67. GMCT1.8P (E300h): Gamma Correction Characteristics Setting (1.8 + )................................................................................ 168
5.3.68. GMCT1.8N (E400h): Gamma Correction Characteristics Setting (1.8 - ) ................................................................................ 169
5.3.69. GMCT2.5P (E500h): Gamma Correction Characteristics Setting (2.5 + )................................................................................ 170
5.3.70. GMCT2.5N (E600h): Gamma Correction Characteristics Setting (2.5 - ) ................................................................................ 171
5.3.71. GMCT1.0N (E700h): Gamma Correction Characteristics Setting (1.0 + ) ............................................................................... 172
5.3.72. GMCT1.0N (E800h): Gamma Correction Characteristics Setting (1.0 - ) ................................................................................ 173
5.3.73. NVMIN (EB00h): NV Memory Write Mode ............................................................................................................................ 174
5.3.74. DGAMR (EC00h): Digital Gamma Correction Characteristics Setting (Red): .......................................................................... 175
5.3.75. DGAMR (ED00h): Digital Gamma Correction Characteristics Setting (Green): ....................................................................... 176
5.3.76. DGAMB (EE00h): Digital Gamma Correction Characteristics Setting (Blue): ..................................................................... 177
5.3.77. PRG_FLAG (F101h): OTP Program Flag Check ............................................................................................................... 178
6. FUNCTION DESCRIPTIONS................................................................................................................................................................... 179
6.1. INTERFACE TYPE SELECTION .............................................................................................................................................................. 179
6.2. MIPI-DSI INTERFACE ......................................................................................................................................................................... 180
6.2.1. General description ............................................................................................................................................................ 180
6.2.2. Interface level communication............................................................................................................................................ 180
6.2.3. DSI data lanes.................................................................................................................................................................... 185
6.2.4. Packet level communication............................................................................................................................................... 196
6.2.5. Customer-defined generic read data type format............................................................................................................... 207
6.3. MDDI INTERFACE .............................................................................................................................................................................. 208
© ORISE Technology Co., Ltd.
Proprietary & Confidential
5
FEB.22 2012
Preliminary Version 0.8

5 Page





OTM8009A arduino
Preliminary
OTM8009A
3.2. Gamma Correction Circuit
3.2.1. Positive gamma correction circuit
VGMP
64 6-bit
DAC
64 6-bit
DAC
64 6-bit
DAC
0
4
8
Gamma RES1
VSSA
64 6-bit
DAC
64 6-bit
DAC
64 6-bit
DAC
247
251
255
Gamma RES3
Gamma RES2
32 5-bit
DAC
52
32 5-bit
DAC
203
32 5-bit
DAC
32 5-bit
DAC
16 4-bit
DAC
16 4-bit
DAC
16 4-bit
DAC
16 4-bit
DAC
32 5-bit
DAC
32 5-bit
DAC
Gamma RES4
3
VSDP0
VSDP[1:3]
VSDP4
3 VSDP[5:7]
VSDP8
7 VSDP[9:15]
VSDP16
16
7 VSDP[17:23]
VSDP24
24
27 VSDP[25:51]
VSD52
27 VSDP[53:79]
VSDP80
80
27 VSDP[81:107]
VSDP108
108
38 VSDP[109:146]
VSDP147
147
27 VSDP[148:174]
VSDP175
175
27 VSDP[176:202]
VSDP203
27 VSDP[204:230]
VSDP231
231
7 VSDP[232:238]
VSDP239
239
7 VSDP[240:246]
VSDP247
3 VSDP[248:250]
VSDP251
3 VSDP[252:254]
VSDP255
© ORISE Technology Co., Ltd.
Proprietary & Confidential
11
FEB.22, 2012
Preliminary Version 0.8

11 Page







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