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PDF 25L1606E Data sheet ( Hoja de datos )
| Número de pieza | 25L1606E | |
| Descripción | MX25L1606E | |
| Fabricantes | MXIC | |
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MX25L8006E
MX25L1606E
MX25L8006E, MX25L1606E
DATASHEET
P/N: PM1548
REV. 1.2, JUL. 02, 2010
1
1 page  
MX25L8006E
MX25L1606E
FEATURES
8M-BIT [x 1 / x 2] CMOS SERIAL FLASH
16M-BIT [x 1 / x 2] CMOS SERIAL FLASH
GENERAL
• Single Power Supply Operation
- 2.7 to 3.6 volt for read, erase, and program operations
• Serial Peripheral Interface compatible -- Mode 0 and Mode 3
• 8M: 8,388,608 x 1 bit structure or 4,194,304 x 2 bits (Dual Output mode) structure
16M: 16,777,216 x 1 bit structure or 8,388,608 x 2 bits (Dual Output mode) structure
• 256 Equal Sectors with 4K byte each (8Mb)
512 Equal Sectors with 4K byte each (16Mb)
- Any Sector can be erased individually
• 16 Equal Blocks with 64K byte each (8Mb)
32 Equal Blocks with 64K byte each (16Mb)
- Any Block can be erased individually
• Program Capability
- Byte base
- Page base (256 bytes)
• Latch-up protected to 100mA from -1V to Vcc +1V
PERFORMANCE
• High Performance
- Fast access time: 86MHz serial clock
- Serial clock of Dual Output mode : 80MHz
- Fast program time: 1.4ms(typ.) and 5ms(max.)/page
- Byte program time: 9us (typical)
- Fast erase time: 60ms(typ.) /sector ; 0.7s(typ.) /block
• Low Power Consumption
- Low active read current: 16Mb: 25mA(max.) at 86MHz; 8Mb: 12mA(max.) at 86MHz
- Low active programming current: 20mA (max.)
- Low active erase current: 20mA (max.)
- Low standby current: 25uA (max.)
- Deep power-down mode 5uA (typical)
• Typical 100,000 erase/program cycles
• 20 years of data retention
SOFTWARE FEATURES
• Input Data Format
- 1-byte Command code
• Advanced Security Features
- Block lock protection
The BP3-BP0(16Mb) ; BP2-BP0(8Mb) status bit defines the size of the area to be software protection against
program and erase instructions
- Additional 512 bit secured OTP for unique identifier
• Auto Erase and Auto Program Algorithm
- Automatically erases and verifies data at selected sector
- Automatically programs and verifies data at selected page by an internal algorithm that automatically times the
program pulse widths (Any page to be programed should have page in the erased state first)
P/N: PM1548
REV. 1.2, JUL. 02, 2010
5
5 Page 
MX25L8006E
MX25L1606E
DATA PROTECTION
The device is designed to offer protection against accidental erasure or programming caused by spurious system
level signals that may exist during power transition. During power up the device automatically resets the state ma-
chine in the standby mode. In addition, with its control register architecture, alteration of the memory contents only
occurs after successful completion of specific command sequences. The device also incorporates several features
to prevent inadvertent write cycles resulting from VCC power-up and power-down transition or system noise.
• Valid command length checking: The command length will be checked whether it is at byte base and completed
on byte boundary.
• Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before
other command to change data. The WEL bit will return to reset stage under following situation:
- Power-up
- Write Disable (WRDI) command completion
- Write Status Register (WRSR) command completion
- Page Program (PP) command completion
- Sector Erase (SE) command completion
- Block Erase (BE) command completion
- Chip Erase (CE) command completion
• Deep Power Down Mode: By entering deep power down mode, the flash device also is under protected from
writing all commands except Release from deep power down mode command (RDP) and Read Electronic Sig-
nature command (RES).
• Advanced Security Features: there are some protection and security features which protect content from inad-
vertent write and hostile access.
I. Block lock protection
- The Software Protected Mode (SPM):
MX25L8006E: use (BP2, BP1, BP0) bits to allow part of memory to be protected as read only. The proected area
definition is shown as table of "Protected Area Sizes", the protected areas are more flexible which may protect
various area by setting value of BP0-BP2 bits.
MX25L1606E: use (BP3, BP2, BP1, BP0) bits to allow part of memory to be protected as read only. The proect-
ed area definition is shown as table of "Protected Area Sizes", the protected areas are more flexible which may
protect various area by setting value of BP0-BP3 bits.
Please refer to table of "protected area sizes".
- The Hardware Proteced Mode (HPM) uses WP# to protect the MX25L8006E:BP2-BP0 / MX25L1606E:BP3-
BP0 bits and SRWD bit.
P/N: PM1548
REV. 1.2, JUL. 02, 2010
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet 25L1606E.PDF ] | |
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